diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 6023519d..31356696 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -184,47 +184,47 @@ add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0 -add wave -noupdate -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState -add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn -add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength -add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH -add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength -add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/OFFSETWIDTH -add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/WORDSPERLINE -add wave -noupdate -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/LOGWPL -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable -add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData -add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit -add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid -add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag -add wave -noupdate -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine -add wave -noupdate -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData -add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF -add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD -add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen -add wave -noupdate -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD -add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF -add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF -add wave -noupdate -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF +add wave -noupdate -expand -group icache -color Orange /testbench/dut/hart/ifu/icache/controller/CurrState +add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn +add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn +add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/NUMLINES +add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKLEN +add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/BLOCKBYTELEN +add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/OFFSETLEN +add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/INDEXLEN +add wave -noupdate -expand -group icache -expand -group {icache parameters} -radix unsigned /testbench/dut/hart/ifu/icache/cachemem/TAGLEN +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCount +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrPAdrF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrInF +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable +add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteData +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValidBit +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataValid +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/DataTag +add wave -noupdate -expand -group icache -expand -group memory -group {tag read} /testbench/dut/hart/ifu/icache/cachemem/cachetags/ReadData +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteEnable +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/WriteLine +add wave -noupdate -expand -group icache -expand -group memory -group {tag write} /testbench/dut/hart/ifu/icache/cachemem/cachetags/StoredData +add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF +add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/AlignedInstrRawD +add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/FlushDLastCyclen +add wave -noupdate -expand -group icache -expand -group {instr to cpu} /testbench/dut/hart/ifu/icache/controller/InstrRawD +add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPF +add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPreFinalF +add wave -noupdate -expand -group icache -expand -group pc /testbench/dut/hart/ifu/icache/controller/PCPFinalF add wave -noupdate -group AHB /testbench/dut/hart/ebu/BusState add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA @@ -245,7 +245,7 @@ add wave -noupdate -group csr -color Aquamarine -label {br executed} -radix unsi add wave -noupdate -group csr -color Aquamarine -label {br miss predicted} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} add wave -noupdate -group csr -childformat {{{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} -radix unsigned} {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} -radix unsigned}} -subitemconfig {{/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[5]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW[4]} {-height 16 -radix unsigned}} /testbench/dut/hart/priv/csr/genblk1/counters/genblk2/HPMCOUNTER_REGW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {2172501 ns} 0} +WaveRestoreCursors {{Cursor 4} {32648010 ns} 0} {{Cursor 5} {759692 ns} 0} quietly wave cursor active 2 configure wave -namecolwidth 250 configure wave -valuecolwidth 189 @@ -261,4 +261,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {391986 ns} +WaveRestoreZoom {1826338 ns} {1988889 ns} diff --git a/wally-pipelined/src/cache/ICacheMem.sv b/wally-pipelined/src/cache/ICacheMem.sv index f394b673..4ea3d22a 100644 --- a/wally-pipelined/src/cache/ICacheMem.sv +++ b/wally-pipelined/src/cache/ICacheMem.sv @@ -3,77 +3,45 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) ( // Pipeline stuff - input logic clk, - input logic reset, + input logic clk, + input logic reset, // If flush is high, invalidate the entire cache - input logic flush, + input logic flush, - // Select which address to read (broken for efficiency's sake) - input logic [`XLEN-1:0] PCTagF, // physical tag address - input logic [`XLEN-1:0] PCNextIndexF, - // Write new data to the cache - input logic WriteEnable, - input logic [BLOCKLEN-1:0] WriteLine, - // Output the word, as well as if it is valid - output logic [31:0] DataWord, // *** was `XLEN-1 - output logic DataValid + input logic [`XLEN-1:0] PCTagF, // physical address + input logic [`XLEN-1:0] PCNextIndexF, // virtual address + input logic WriteEnable, + input logic [BLOCKLEN-1:0] WriteLine, + output logic [BLOCKLEN-1:0] ReadLineF, + output logic HitF ); - // divide the address bus into sections, tag, index, offset + // divide the address bus into sections; tag, index, and offset localparam BLOCKBYTELEN = BLOCKLEN/8; localparam OFFSETLEN = $clog2(BLOCKBYTELEN); localparam INDEXLEN = $clog2(NUMLINES); + // *** BUG. `XLEN needs to be replaced with the virtual address width, S32, S39, or S48 localparam TAGLEN = `XLEN - OFFSETLEN - INDEXLEN; - // Machinery to read from and write to the correct addresses in memory - logic [BLOCKLEN-1:0] ReadLine; - - // Machinery to check if a given read is valid and is the desired value - logic [TAGLEN-1:0] DataTag; - logic [NUMLINES-1:0] ValidOut; - logic DataValidBit; + logic [TAGLEN-1:0] LookupTag; + logic [NUMLINES-1:0] ValidOut; + logic DataValidBit; // Depth is number of bits in one "word" of the memory, width is number of such words sram1rw #(.DEPTH(BLOCKLEN), .WIDTH(NUMLINES)) cachemem (.*, .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .ReadData(ReadLine), + .ReadData(ReadLineF), .WriteData(WriteLine) ); + sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES)) cachetags (.*, .Addr(PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .ReadData(DataTag), + .ReadData(LookupTag), .WriteData(PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]) ); - // Pick the right bits coming out the read line - //assign DataWord = ReadLineTransformed[ReadOffset]; - //logic [31:0] tempRD; - always_comb begin - case (PCTagF[4:1]) - 0: DataWord = ReadLine[31:0]; - 1: DataWord = ReadLine[47:16]; - 2: DataWord = ReadLine[63:32]; - 3: DataWord = ReadLine[79:48]; - - 4: DataWord = ReadLine[95:64]; - 5: DataWord = ReadLine[111:80]; - 6: DataWord = ReadLine[127:96]; - 7: DataWord = ReadLine[143:112]; - - 8: DataWord = ReadLine[159:128]; - 9: DataWord = ReadLine[175:144]; - 10: DataWord = ReadLine[191:160]; - 11: DataWord = ReadLine[207:176]; - - 12: DataWord = ReadLine[223:192]; - 13: DataWord = ReadLine[239:208]; - 14: DataWord = ReadLine[255:224]; - 15: DataWord = {16'b0, ReadLine[255:240]}; - endcase - end - // Correctly handle the valid bits always_ff @(posedge clk, posedge reset) begin if (reset) begin @@ -87,5 +55,5 @@ module ICacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256) end DataValidBit <= ValidOut[PCNextIndexF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]]; end - assign DataValid = DataValidBit && (DataTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]); + assign HitF = DataValidBit && (LookupTag == PCTagF[`XLEN-1:INDEXLEN+OFFSETLEN]); endmodule diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 3f226bb2..e3a0829b 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -25,58 +25,86 @@ `include "wally-config.vh" -module icache( - // Basic pipeline stuff - input logic clk, reset, - input logic StallF, StallD, - input logic FlushD, - input logic [`XLEN-1:0] PCNextF, - input logic [`XLEN-1:0] PCPF, - // Data read in from the ebu unit - input logic [`XLEN-1:0] InstrInF, - input logic InstrAckF, - // Read requested from the ebu unit - output logic [`XLEN-1:0] InstrPAdrF, - output logic InstrReadF, - // High if the instruction currently in the fetch stage is compressed - output logic CompressedF, - // High if the icache is requesting a stall - output logic ICacheStallF, - // The raw (not decompressed) instruction that was requested - // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros - output logic [31:0] InstrRawD -); +module icache + ( + // Basic pipeline stuff + input logic clk, reset, + input logic StallF, StallD, + input logic FlushD, + input logic [`XLEN-1:0] PCNextF, + input logic [`XLEN-1:0] PCPF, + // Data read in from the ebu unit + input logic [`XLEN-1:0] InstrInF, + input logic InstrAckF, + // Read requested from the ebu unit + output logic [`XLEN-1:0] InstrPAdrF, + output logic InstrReadF, + // High if the instruction currently in the fetch stage is compressed + output logic CompressedF, + // High if the icache is requesting a stall + output logic ICacheStallF, + // The raw (not decompressed) instruction that was requested + // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros + output logic [31:0] InstrRawD + ); - // Configuration parameters - // TODO Move these to a config file - localparam integer BLOCKLEN = 256; - localparam integer NUMLINES = 512; + // Configuration parameters + // TODO Move these to a config file + localparam integer BLOCKLEN = 256; + localparam integer NUMLINES = 512; - // Input signals to cache memory - logic FlushMem; - logic ICacheMemWriteEnable; - logic [BLOCKLEN-1:0] ICacheMemWriteData; - logic EndFetchState; - logic [`XLEN-1:0] PCTagF, PCNextIndexF; - // Output signals from cache memory - logic [31:0] ICacheMemReadData; - logic ICacheMemReadValid; - logic ICacheReadEn; + // Input signals to cache memory + logic FlushMem; + logic ICacheMemWriteEnable; + logic [BLOCKLEN-1:0] ICacheMemWriteData; + logic EndFetchState; + logic [`XLEN-1:0] PCTagF, PCNextIndexF; + // Output signals from cache memory + logic [31:0] ICacheMemReadData; + logic ICacheMemReadValid; + logic ICacheReadEn; + logic [BLOCKLEN-1:0] ReadLineF; + ICacheMem #(.BLOCKLEN(BLOCKLEN), .NUMLINES(NUMLINES)) cachemem( - .*, - // Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall - .flush(FlushMem), - .WriteEnable(ICacheMemWriteEnable), - .WriteLine(ICacheMemWriteData), - .DataWord(ICacheMemReadData), - .DataValid(ICacheMemReadValid) - ); + .*, + // Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall + .flush(FlushMem), + .WriteEnable(ICacheMemWriteEnable), + .WriteLine(ICacheMemWriteData), + .ReadLineF(ReadLineF), + .HitF(ICacheMemReadValid) + ); - ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.*); + always_comb begin + case (PCTagF[4:1]) + 0: ICacheMemReadData = ReadLineF[31:0]; + 1: ICacheMemReadData = ReadLineF[47:16]; + 2: ICacheMemReadData = ReadLineF[63:32]; + 3: ICacheMemReadData = ReadLineF[79:48]; - // For now, assume no writes to executable memory - assign FlushMem = 1'b0; + 4: ICacheMemReadData = ReadLineF[95:64]; + 5: ICacheMemReadData = ReadLineF[111:80]; + 6: ICacheMemReadData = ReadLineF[127:96]; + 7: ICacheMemReadData = ReadLineF[143:112]; + + 8: ICacheMemReadData = ReadLineF[159:128]; + 9: ICacheMemReadData = ReadLineF[175:144]; + 10: ICacheMemReadData = ReadLineF[191:160]; + 11: ICacheMemReadData = ReadLineF[207:176]; + + 12: ICacheMemReadData = ReadLineF[223:192]; + 13: ICacheMemReadData = ReadLineF[239:208]; + 14: ICacheMemReadData = ReadLineF[255:224]; + 15: ICacheMemReadData = {16'b0, ReadLineF[255:240]}; + endcase + end + + + ICacheCntrl #(.BLOCKLEN(BLOCKLEN)) controller(.*); + + // For now, assume no writes to executable memory + assign FlushMem = 1'b0; endmodule