From 183a2dcfb56276ea9c52f665c3be9ae32799911e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 10 Feb 2021 01:43:54 -0500
Subject: [PATCH] Debugging bus interface.

---
 wally-pipelined/src/ebu/ahblite.sv             | 7 +++++--
 wally-pipelined/src/hazard/hazard.sv           | 2 +-
 wally-pipelined/testbench/testbench-imperas.sv | 1 +
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index ce54a21f..36882428 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -110,6 +110,7 @@ module ahblite (
     if (MemReadM) NextAdrState = MEMREAD;
     else if (MemWriteM) NextAdrState = MEMWRITE;
     else if (InstrReadF) NextAdrState = INSTRREAD;
+//    else if (1) NextAdrState = INSTRREAD; // dm 2/9/2021 testing
     else NextAdrState = IDLE;
   
   // Generate acknowledges based on bus state and ready
@@ -159,8 +160,10 @@ module ahblite (
     else InstrState <= NextInstrState;*/
 
   assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM  && ~MemWriteM && InstrReadF)) || 
-                          (InstrState == 1 && ~InstrAckD) ||
-                          (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing 
+                          (InstrState == 1 && ~InstrAckD)  ||
+                          (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later 
+/*  assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM  && ~MemWriteM)) || 
+                          (InstrState == 1 && ~InstrAckD);  // *** removed InstrReadF above dh 2/9/20 */
   assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better
   // temporarily turn off stalls and check it works
   //assign DataStall = 0;
diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv
index 7c4afd6f..88d78ee4 100644
--- a/wally-pipelined/src/hazard/hazard.sv
+++ b/wally-pipelined/src/hazard/hazard.sv
@@ -61,7 +61,7 @@ module hazard(
   assign StallDCause = LoadStallD;                       // stall in decode if instruction is a load dependent on previous
   assign StallECause = 0;
   assign StallMCause = 0; // sDataStall; // not yet used***
-  assign StallWCause = DataStall;
+  assign StallWCause = DataStall; // | InstrStall;
 
   // Each stage stalls if the next stage is stalled or there is a cause to stall this stage.
   assign StallF = StallD | StallFCause;
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index 98c17616..cad2d68d 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -75,6 +75,7 @@ string tests64iNOc[] = {
                      "rv64i/I-MISALIGN_JMP-01","2000"
   };
  string tests64i[] = '{                 
+                     "rv64i/I-ENDIANESS-01", "2010",
                      "rv64i/I-ADD-01", "3000",
                      "rv64i/I-ADDI-01", "3000",
                      "rv64i/I-ADDIW-01", "3000",