From 17c0f9629acf1a65a8b0dd1da5c9624fb8b0a9fe Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 9 Mar 2021 09:28:25 -0500 Subject: [PATCH] WALLY-LRSC atomic test passing --- wally-pipelined/config/rv64ic/wally-config.vh | 4 +-- wally-pipelined/regression/wally-pipelined.do | 2 +- wally-pipelined/src/dmem/dmem.sv | 2 +- wally-pipelined/src/ieu/controller.sv | 2 +- .../testbench/testbench-imperas.sv | 36 +++++++++++++++++-- 5 files changed, 38 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 4a9c303d..e5240e8b 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -27,8 +27,8 @@ // RV32 or RV64: XLEN = 32 or 64 `define XLEN 64 -//`define MISA (32'h00000104) -`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) +//`define MISA (32'h00000105) +`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) `define A_SUPPORTED ((`MISA >> 0) % 2 == 1) `define C_SUPPORTED ((`MISA >> 2) % 2 == 1) `define D_SUPPORTED ((`MISA >> 3) % 2 == 1) diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index 813374ef..94a2bef2 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -113,6 +113,6 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -#run 2000 +#run 4100 run -all #quit diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index aa4327c2..547663fc 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -100,7 +100,7 @@ module dmem ( assign lrM = MemReadM && AtomicM; assign scM = MemRWM[0] && AtomicM; - assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM == ReservationPAdrW) && ReservationValidW; + assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`XLEN-1:2] == ReservationPAdrW) && ReservationValidW; assign SquashSCM = scM && ~WriteAdrMatchM; always_comb begin // ReservationValidM (next valiue of valid reservation) if (lrM) ReservationValidM = 1; // set valid on load reserve diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 7721dc91..dc4f16d5 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -116,7 +116,7 @@ module controller( if (InstrD[31:27] == 5'b00010) ControlsD = 22'b1_000_00_10_001_0_00_0_0_0_0_0_0_1_0; // lr else if (InstrD[31:27] == 5'b00011) - ControlsD = 22'b1_101_01_01_110_0_00_0_0_0_0_0_0_1_0; // sc + ControlsD = 22'b1_101_01_01_101_0_00_0_0_0_0_0_0_1_0; // sc else ControlsD = 22'b0_000_00_00_000_0_00_0_0_0_0_0_0_1_0; // other atomic; decode later end else diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 78ee5810..50ef7c93 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -37,6 +37,9 @@ module testbench(); string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; //logic [31:0] InstrW; logic [`XLEN-1:0] meminit; + string tests64a[] = '{ + "rv64a/WALLY-LRSC", "2110" + }; string tests64m[] = '{ "rv64m/I-MUL-01", "3000", "rv64m/I-MULH-01", "3000", @@ -322,9 +325,11 @@ string tests32i[] = { initial if (`XLEN == 64) begin // RV64 tests = {tests64i}; - if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic}; - else tests = {tests, tests64iNOc}; - if (`M_SUPPORTED % 2 == 1) tests = {tests, tests64m}; + if (`C_SUPPORTED) tests = {tests, tests64ic}; + else tests = {tests, tests64iNOc}; + if (`M_SUPPORTED) tests = {tests, tests64m}; + if (`A_SUPPORTED) tests = {tests64a, tests}; + // tests = {tests64a, tests}; end else begin // RV32 tests = {tests32i}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; @@ -368,6 +373,7 @@ string tests32i[] = { memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); + $display("Read memfile %s", memfilename); reset = 1; # 42; reset = 0; end @@ -584,6 +590,30 @@ module instrNameDecTB( 10'b1110011_101: name = "CSRRWI"; 10'b1110011_110: name = "CSRRSI"; 10'b1110011_111: name = "CSRRCI"; + 10'b0101111_010: if (funct7[6:2] == 5'b00010) name = "LR.W"; + else if (funct7[6:2] == 5'b00011) name = "SC.W"; + else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.W"; + else if (funct7[6:2] == 5'b00000) name = "AMOADD.W"; + else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.W"; + else if (funct7[6:2] == 5'b01100) name = "AMOAND.W"; + else if (funct7[6:2] == 5'b01000) name = "AMOOR.W"; + else if (funct7[6:2] == 5'b10000) name = "AMOMIN.W"; + else if (funct7[6:2] == 5'b10100) name = "AMOMAX.W"; + else if (funct7[6:2] == 5'b11000) name = "AMOMINU.W"; + else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.W"; + else name = "ILLEGAL"; + 10'b0101111_011: if (funct7[6:2] == 5'b00010) name = "LR.D"; + else if (funct7[6:2] == 5'b00011) name = "SC.D"; + else if (funct7[6:2] == 5'b00001) name = "AMOSWAP.D"; + else if (funct7[6:2] == 5'b00000) name = "AMOADD.D"; + else if (funct7[6:2] == 5'b00100) name = "AMOAXOR.D"; + else if (funct7[6:2] == 5'b01100) name = "AMOAND.D"; + else if (funct7[6:2] == 5'b01000) name = "AMOOR.D"; + else if (funct7[6:2] == 5'b10000) name = "AMOMIN.D"; + else if (funct7[6:2] == 5'b10100) name = "AMOMAX.D"; + else if (funct7[6:2] == 5'b11000) name = "AMOMINU.D"; + else if (funct7[6:2] == 5'b11100) name = "AMOMAXU.D"; + else name = "ILLEGAL"; 10'b0001111_???: name = "FENCE"; default: name = "ILLEGAL"; endcase