From 15f6871a8dacfca2d26e9a898ece0e9d8deff896 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 22 Feb 2022 22:45:00 -0600 Subject: [PATCH] Added generates to pcnextf muxes for privileged and caches. --- pipelined/src/ifu/ifu.sv | 26 +++++++++++++++++++------- pipelined/src/lsu/busdp.sv | 10 +++++----- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 58eceb7c..663639f8 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -76,7 +76,6 @@ module ifu ( input logic [1:0] STATUS_MPP, input logic ITLBWriteF, ITLBFlushF, output logic ITLBMissF, InstrDAPageFaultF, - // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], output logic InstrAccessFaultF, @@ -120,7 +119,7 @@ module ifu ( assign PCFExt = {2'b00, PCFSpill}; ///////////////////////////////////////////////////////////////////////////////////////////// - // Spill Support *** add other banners + // Spill Support ///////////////////////////////////////////////////////////////////////////////////////////// if(`C_SUPPORTED) begin : SpillSupport @@ -247,18 +246,28 @@ module ifu ( flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD); + //////////////////////////////////////////////////////////////////////////////////////////////// + // PCNextF logic + //////////////////////////////////////////////////////////////////////////////////////////////// + assign PrivilegedChangePCM = RetM | TrapM; - // *** look at moves pcmux2 and pcmux3 to generates as they are needed only on supporting caches and - // privilege instructions respectively. mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); - mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F)); - mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); + if(CACHE_ENABLED) + mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), + .y(PCNext2F)); + else assign PCNext2F = PCNext1F; + if(`ZICSR_SUPPORTED) + mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), + .y(UnalignedPCNextF)); + else assign UnalignedPCNextF = PCNext2F; assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); - // branch and jump predictor + //////////////////////////////////////////////////////////////////////////////////////////////// + // Branch and Jump Predictor + //////////////////////////////////////////////////////////////////////////////////////////////// if (`BPRED_ENABLED) begin : bpred logic BPPredWrongM; logic SelBPPredF; @@ -295,6 +304,9 @@ module ifu ( else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 + //////////////////////////////////////////////////////////////////////////////////////////////// + // Decode stage pipeline register and compressed instruction decoding. + //////////////////////////////////////////////////////////////////////////////////////////////// // Decode stage pipeline register and logic flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 0c172037..66e41675 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -67,17 +67,17 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; - logic [`PA_BITS-1:0] LocalLSUBusAdr; genvar index; - for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer - flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)), - .d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); + logic [WORDSPERLINE-1:0] CaptureWord; + assign CaptureWord[index] = LSUBusAck & LSUBusRead & (index == WordCount); + flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), + .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); end mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; - mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), + mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(LSUBusSize)); busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED)