diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index 4b61f2bf..313e2343 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -36,7 +36,7 @@ module fhazard( input logic [4:0] RdM, RdW, // the adress being written to input logic [1:0] FResSelM, // the result being selected input logic XEnE, YEnE, ZEnE, - output logic FStallD, // stall the decode stage + output logic FPUStallD, // stall the decode stage output logic [1:0] ForwardXE, ForwardYE, ForwardZE // select a forwarded value ); @@ -46,14 +46,14 @@ module fhazard( ForwardXE = 2'b00; // choose FRD1E ForwardYE = 2'b00; // choose FRD2E ForwardZE = 2'b00; // choose FRD3E - FStallD = 0; + FPUStallD = 0; // if the needed value is in the memory stage - input 1 if(XEnE) if ((Adr1E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM - else FStallD = 1; // otherwise stall + else FPUStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W @@ -63,7 +63,7 @@ module fhazard( if ((Adr2E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM - else FStallD = 1; // otherwise stall + else FPUStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W @@ -73,7 +73,7 @@ module fhazard( if ((Adr3E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM - else FStallD = 1; // otherwise stall + else FPUStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 65992a26..4b73a71b 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -46,7 +46,7 @@ module fpu ( input logic MDUE, W64E, output logic FRegWriteM, // FP register write enable (to privileged unit) output logic FpLoadStoreM, // Fp load instruction? (to LSU) - output logic FStallD, // Stall the decode stage (To HZU) + output logic FPUStallD, // Stall the decode stage (To HZU) output logic FWriteIntE, // integer register write enable (to IEU) output logic FCvtIntE, // Convert to int (to IEU) output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) @@ -201,7 +201,7 @@ module fpu ( // Hazard unit for FPU // - determines if any forwarding or stalls are needed fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResSelM, - .XEnE, .YEnE(YEnForwardE), .ZEnE(ZEnForwardE), .FStallD, .ForwardXE, .ForwardYE, .ForwardZE); + .XEnE, .YEnE(YEnForwardE), .ZEnE(ZEnForwardE), .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE); // forwarding muxs mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE); diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0b7cbc64..f38ef77f 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -35,7 +35,7 @@ module hazard( (* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFenceM, RetM, TrapM, (* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, (* mark_debug = "true" *) input logic LSUStallM, IFUStallF, -(* mark_debug = "true" *) input logic FCvtIntStallD, FStallD, +(* mark_debug = "true" *) input logic FCvtIntStallD, FPUStallD, (* mark_debug = "true" *) input logic DivBusyE,FDivBusyE, (* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM, (* mark_debug = "true" *) input logic wfiM, IntPendingM, @@ -70,7 +70,7 @@ module hazard( assign StallFCause = '0; // stall in decode if instruction is a load/mul/csr dependent on previous - assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~FlushDCause; + assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause; assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index f2ff2a7e..ef6cdc1e 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -86,7 +86,7 @@ module wallypipelinedcore ( // floating point unit signals logic [2:0] FRM_REGW; logic [4:0] RdM, RdW; - logic FStallD; + logic FPUStallD; logic FWriteIntE; logic [`FLEN-1:0] FWriteDataM; logic [`XLEN-1:0] FIntResM; @@ -320,7 +320,7 @@ module wallypipelinedcore ( .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM, .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, .LSUStallM, .IFUStallF, - .FCvtIntStallD, .FStallD, + .FCvtIntStallD, .FPUStallD, .DivBusyE, .FDivBusyE, .EcallFaultM, .BreakpointFaultM, .wfiM, .IntPendingM, @@ -398,7 +398,7 @@ module wallypipelinedcore ( .FpLoadStoreM, .ForwardedSrcBE, // Integer input for intdiv .Funct3E, .Funct3M, .MDUE, .W64E, // Integer flags and functions - .FStallD, // Stall the decode stage + .FPUStallD, // Stall the decode stage .FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation .FWriteDataM, // Data to be written to memory .FIntResM, // data to be written to integer register @@ -410,7 +410,7 @@ module wallypipelinedcore ( .FPIntDivResultW ); // floating point unit end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low - assign FStallD = 0; + assign FPUStallD = 0; assign FWriteIntE = 0; assign FCvtIntE = 0; assign FIntResM = 0;