From 1510c2d92fe483a6c2222357821af7412a073a4f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 24 Oct 2022 15:38:39 -0500
Subject: [PATCH] Setup to run with both the vcu108 and vcu118 boards.  Set the
 parameters in the Makefile.

---
 fpga/constraints/constraints-vcu108.xdc       | 263 ++++++++++++++++++
 ...constraints.xdc => constraints-vcu118.xdc} |   0
 fpga/generator/Makefile                       |  12 +-
 .../dcache-miss-evict-dirty-deadlock.tsm      |   0
 fpga/generator/{ => debug}/load-deadlock.tsm  |   0
 fpga/generator/debug/miss-fetch-deadlock.tsm  |  37 +++
 fpga/generator/{ => debug}/trigger.tsm        |   0
 fpga/generator/debug/uart-stuck.tsm           |  49 ++++
 fpga/generator/wally.tcl                      |  10 +-
 fpga/generator/xlnx_ahblite_axi_bridge.tcl    |   8 +-
 fpga/generator/xlnx_axi_clock_converter.tcl   |   8 +-
 fpga/generator/xlnx_ddr4-vcu108.tcl           | 164 +++++++++++
 fpga/generator/xlnx_ddr4-vcu118.tcl           | 165 +++++++++++
 fpga/generator/xlnx_ddr4.tcl                  |  12 +-
 fpga/generator/xlnx_proc_sys_reset.tcl        |   8 +-
 pipelined/src/uncore/uartPC16550D.sv          |   3 +-
 16 files changed, 715 insertions(+), 24 deletions(-)
 create mode 100644 fpga/constraints/constraints-vcu108.xdc
 rename fpga/constraints/{constraints.xdc => constraints-vcu118.xdc} (100%)
 rename fpga/generator/{ => debug}/dcache-miss-evict-dirty-deadlock.tsm (100%)
 rename fpga/generator/{ => debug}/load-deadlock.tsm (100%)
 create mode 100644 fpga/generator/debug/miss-fetch-deadlock.tsm
 rename fpga/generator/{ => debug}/trigger.tsm (100%)
 create mode 100644 fpga/generator/debug/uart-stuck.tsm
 create mode 100644 fpga/generator/xlnx_ddr4-vcu108.tcl
 create mode 100644 fpga/generator/xlnx_ddr4-vcu118.tcl

diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc
new file mode 100644
index 00000000..cbb70db9
--- /dev/null
+++ b/fpga/constraints/constraints-vcu108.xdc
@@ -0,0 +1,263 @@
+# The main clocks are all autogenerated by the Xilinx IP
+# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
+# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
+# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
+
+create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
+
+##### GPI ####
+set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
+set_property PACKAGE_PIN M22 [get_ports {GPI[1]}]
+set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}]
+set_property PACKAGE_PIN A10 [get_ports {GPI[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
+set_max_delay -from [get_ports {GPI[*]}] 10.000
+
+##### GPO #### 
+set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
+set_property PACKAGE_PIN AV34 [get_ports {GPO[1]}]
+set_property PACKAGE_PIN AY30 [get_ports {GPO[2]}]
+set_property PACKAGE_PIN BF32 [get_ports {GPO[4]}]
+set_property PACKAGE_PIN BB32 [get_ports {GPO[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
+set_max_delay -to [get_ports {GPO[*]}] 10.000
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
+
+
+##### UART #####
+set_property PACKAGE_PIN BC24 [get_ports UARTSin]
+set_property PACKAGE_PIN BE24 [get_ports UARTSout]
+set_max_delay -from [get_ports UARTSin] 10.000
+set_max_delay -to [get_ports UARTSout] 10.000
+set_property IOSTANDARD LVCMOS18 [get_ports UARTSin]
+set_property IOSTANDARD LVCMOS18 [get_ports UARTSout]
+# set_property DRIVE 6 [get_ports UARTSout]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
+
+
+##### reset #####
+set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
+set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
+set_max_delay -from [get_ports reset] 15.000
+set_false_path -from [get_ports reset]
+set_property PACKAGE_PIN E34 [get_ports {reset}]
+set_property IOSTANDARD LVCMOS12 [get_ports {reset}]
+
+
+
+##### cpu_reset #####
+set_property PACKAGE_PIN AY35 [get_ports {cpu_reset}]
+set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
+
+
+##### calib #####
+set_property PACKAGE_PIN BA37 [get_ports calib]
+set_property IOSTANDARD LVCMOS12 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
+set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
+
+
+##### ahblite_resetn #####
+set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
+set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
+
+
+##### south_rst #####
+set_property PACKAGE_PIN D9 [get_ports south_rst]
+set_property IOSTANDARD LVCMOS12 [get_ports south_rst]
+set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
+set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
+
+
+##### SD Card I/O #####
+set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
+set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}]
+set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}]
+set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
+set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
+set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
+set_property PULLUP true [get_ports {SDCDat[3]}]
+set_property PULLUP true [get_ports {SDCDat[2]}]
+set_property PULLUP true [get_ports {SDCDat[1]}]
+set_property PULLUP true [get_ports {SDCDat[0]}]
+set_property PULLUP true [get_ports {SDCCmd}]
+
+
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
+
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
+set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
+
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
+set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
+
+set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
+
+
+
+set_property DCI_CASCADE {64} [get_iobanks 65]
+set_property INTERNAL_VREF 0.9 [get_iobanks 65]
+
+
+set_property PACKAGE_PIN E33 [get_ports c0_ddr4_act_n]
+set_property PACKAGE_PIN C30 [get_ports {c0_ddr4_adr[0]}]
+set_property PACKAGE_PIN A31 [get_ports {c0_ddr4_adr[10]}]
+set_property PACKAGE_PIN A33 [get_ports {c0_ddr4_adr[11]}]
+set_property PACKAGE_PIN F29 [get_ports {c0_ddr4_adr[12]}]
+set_property PACKAGE_PIN B32 [get_ports {c0_ddr4_adr[13]}]
+set_property PACKAGE_PIN D29 [get_ports {c0_ddr4_adr[14]}]
+set_property PACKAGE_PIN B31 [get_ports {c0_ddr4_adr[15]}]
+set_property PACKAGE_PIN B33 [get_ports {c0_ddr4_adr[16]}]
+set_property PACKAGE_PIN D32 [get_ports {c0_ddr4_adr[1]}]
+set_property PACKAGE_PIN B30 [get_ports {c0_ddr4_adr[2]}]
+set_property PACKAGE_PIN C33 [get_ports {c0_ddr4_adr[3]}]
+set_property PACKAGE_PIN E32 [get_ports {c0_ddr4_adr[4]}]
+set_property PACKAGE_PIN A29 [get_ports {c0_ddr4_adr[5]}]
+set_property PACKAGE_PIN C29 [get_ports {c0_ddr4_adr[6]}]
+set_property PACKAGE_PIN E29 [get_ports {c0_ddr4_adr[7]}]
+set_property PACKAGE_PIN A30 [get_ports {c0_ddr4_adr[8]}]
+set_property PACKAGE_PIN C32 [get_ports {c0_ddr4_adr[9]}]
+set_property PACKAGE_PIN G30 [get_ports {c0_ddr4_ba[0]}]
+set_property PACKAGE_PIN F30 [get_ports {c0_ddr4_ba[1]}]
+set_property PACKAGE_PIN F33 [get_ports {c0_ddr4_bg[0]}]
+set_property PACKAGE_PIN E31 [get_ports {c0_ddr4_ck_t[0]}]
+set_property PACKAGE_PIN D31 [get_ports {c0_ddr4_ck_c[0]}]
+set_property PACKAGE_PIN K29 [get_ports {c0_ddr4_cke[0]}]
+set_property PACKAGE_PIN D30 [get_ports {c0_ddr4_cs_n[0]}]
+set_property PACKAGE_PIN J37 [get_ports {c0_ddr4_dq[0]}]
+set_property PACKAGE_PIN F35 [get_ports {c0_ddr4_dq[10]}]
+set_property PACKAGE_PIN J35 [get_ports {c0_ddr4_dq[11]}]
+set_property PACKAGE_PIN G37 [get_ports {c0_ddr4_dq[12]}]
+set_property PACKAGE_PIN H35 [get_ports {c0_ddr4_dq[13]}]
+set_property PACKAGE_PIN G36 [get_ports {c0_ddr4_dq[14]}]
+set_property PACKAGE_PIN H37 [get_ports {c0_ddr4_dq[15]}]
+set_property PACKAGE_PIN C39 [get_ports {c0_ddr4_dq[16]}]
+set_property PACKAGE_PIN A38 [get_ports {c0_ddr4_dq[17]}]
+set_property PACKAGE_PIN B40 [get_ports {c0_ddr4_dq[18]}]
+set_property PACKAGE_PIN D40 [get_ports {c0_ddr4_dq[19]}]
+set_property PACKAGE_PIN H40 [get_ports {c0_ddr4_dq[1]}]
+set_property PACKAGE_PIN E38 [get_ports {c0_ddr4_dq[20]}]
+set_property PACKAGE_PIN B38 [get_ports {c0_ddr4_dq[21]}]
+set_property PACKAGE_PIN E37 [get_ports {c0_ddr4_dq[22]}]
+set_property PACKAGE_PIN C40 [get_ports {c0_ddr4_dq[23]}]
+set_property PACKAGE_PIN C34 [get_ports {c0_ddr4_dq[24]}]
+set_property PACKAGE_PIN A34 [get_ports {c0_ddr4_dq[25]}]
+set_property PACKAGE_PIN D34 [get_ports {c0_ddr4_dq[26]}]
+set_property PACKAGE_PIN A35 [get_ports {c0_ddr4_dq[27]}]
+set_property PACKAGE_PIN A36 [get_ports {c0_ddr4_dq[28]}]
+set_property PACKAGE_PIN C35 [get_ports {c0_ddr4_dq[29]}]
+set_property PACKAGE_PIN F38 [get_ports {c0_ddr4_dq[2]}]
+set_property PACKAGE_PIN B35 [get_ports {c0_ddr4_dq[30]}]
+set_property PACKAGE_PIN D35 [get_ports {c0_ddr4_dq[31]}]
+set_property PACKAGE_PIN N27 [get_ports {c0_ddr4_dq[32]}]
+set_property PACKAGE_PIN R27 [get_ports {c0_ddr4_dq[33]}]
+set_property PACKAGE_PIN N24 [get_ports {c0_ddr4_dq[34]}]
+set_property PACKAGE_PIN R24 [get_ports {c0_ddr4_dq[35]}]
+set_property PACKAGE_PIN P24 [get_ports {c0_ddr4_dq[36]}]
+set_property PACKAGE_PIN P26 [get_ports {c0_ddr4_dq[37]}]
+set_property PACKAGE_PIN P27 [get_ports {c0_ddr4_dq[38]}]
+set_property PACKAGE_PIN T24 [get_ports {c0_ddr4_dq[39]}]
+set_property PACKAGE_PIN H39 [get_ports {c0_ddr4_dq[3]}]
+set_property PACKAGE_PIN K27 [get_ports {c0_ddr4_dq[40]}]
+set_property PACKAGE_PIN L26 [get_ports {c0_ddr4_dq[41]}]
+set_property PACKAGE_PIN J27 [get_ports {c0_ddr4_dq[42]}]
+set_property PACKAGE_PIN K28 [get_ports {c0_ddr4_dq[43]}]
+set_property PACKAGE_PIN K26 [get_ports {c0_ddr4_dq[44]}]
+set_property PACKAGE_PIN M25 [get_ports {c0_ddr4_dq[45]}]
+set_property PACKAGE_PIN J26 [get_ports {c0_ddr4_dq[46]}]
+set_property PACKAGE_PIN L28 [get_ports {c0_ddr4_dq[47]}]
+set_property PACKAGE_PIN E27 [get_ports {c0_ddr4_dq[48]}]
+set_property PACKAGE_PIN E28 [get_ports {c0_ddr4_dq[49]}]
+set_property PACKAGE_PIN K37 [get_ports {c0_ddr4_dq[4]}]
+set_property PACKAGE_PIN E26 [get_ports {c0_ddr4_dq[50]}]
+set_property PACKAGE_PIN H27 [get_ports {c0_ddr4_dq[51]}]
+set_property PACKAGE_PIN F25 [get_ports {c0_ddr4_dq[52]}]
+set_property PACKAGE_PIN F28 [get_ports {c0_ddr4_dq[53]}]
+set_property PACKAGE_PIN G25 [get_ports {c0_ddr4_dq[54]}]
+set_property PACKAGE_PIN G27 [get_ports {c0_ddr4_dq[55]}]
+set_property PACKAGE_PIN B28 [get_ports {c0_ddr4_dq[56]}]
+set_property PACKAGE_PIN A28 [get_ports {c0_ddr4_dq[57]}]
+set_property PACKAGE_PIN B25 [get_ports {c0_ddr4_dq[58]}]
+set_property PACKAGE_PIN B27 [get_ports {c0_ddr4_dq[59]}]
+set_property PACKAGE_PIN G40 [get_ports {c0_ddr4_dq[5]}]
+set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[60]}]
+set_property PACKAGE_PIN C27 [get_ports {c0_ddr4_dq[61]}]
+set_property PACKAGE_PIN C25 [get_ports {c0_ddr4_dq[62]}]
+set_property PACKAGE_PIN D26 [get_ports {c0_ddr4_dq[63]}]
+set_property PACKAGE_PIN F39 [get_ports {c0_ddr4_dq[6]}]
+set_property PACKAGE_PIN F40 [get_ports {c0_ddr4_dq[7]}]
+set_property PACKAGE_PIN F36 [get_ports {c0_ddr4_dq[8]}]
+set_property PACKAGE_PIN J36 [get_ports {c0_ddr4_dq[9]}]
+set_property PACKAGE_PIN H38 [get_ports {c0_ddr4_dqs_t[0]}]
+set_property PACKAGE_PIN G38 [get_ports {c0_ddr4_dqs_c[0]}]
+set_property PACKAGE_PIN H34 [get_ports {c0_ddr4_dqs_t[1]}]
+set_property PACKAGE_PIN G35 [get_ports {c0_ddr4_dqs_c[1]}]
+set_property PACKAGE_PIN A39 [get_ports {c0_ddr4_dqs_t[2]}]
+set_property PACKAGE_PIN A40 [get_ports {c0_ddr4_dqs_c[2]}]
+set_property PACKAGE_PIN B36 [get_ports {c0_ddr4_dqs_t[3]}]
+set_property PACKAGE_PIN B37 [get_ports {c0_ddr4_dqs_c[3]}]
+set_property PACKAGE_PIN P25 [get_ports {c0_ddr4_dqs_t[4]}]
+set_property PACKAGE_PIN N25 [get_ports {c0_ddr4_dqs_c[4]}]
+set_property PACKAGE_PIN L24 [get_ports {c0_ddr4_dqs_t[5]}]
+set_property PACKAGE_PIN L25 [get_ports {c0_ddr4_dqs_c[5]}]
+set_property PACKAGE_PIN H28 [get_ports {c0_ddr4_dqs_t[6]}]
+set_property PACKAGE_PIN G28 [get_ports {c0_ddr4_dqs_c[6]}]
+set_property PACKAGE_PIN B26 [get_ports {c0_ddr4_dqs_t[7]}]
+set_property PACKAGE_PIN A26 [get_ports {c0_ddr4_dqs_c[7]}]
+set_property PACKAGE_PIN J31 [get_ports {c0_ddr4_odt[0]}]
+set_property PACKAGE_PIN M28 [get_ports c0_ddr4_reset_n]
+
+
+set_property PACKAGE_PIN J39 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+set_property PACKAGE_PIN F34 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+set_property PACKAGE_PIN E39 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+set_property PACKAGE_PIN D37 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+set_property PACKAGE_PIN T26 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+set_property PACKAGE_PIN M27 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+set_property PACKAGE_PIN G26 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+
+
+
+
+
+set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
+
+
+set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
+set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
+
+
+
+set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
+
diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints-vcu118.xdc
similarity index 100%
rename from fpga/constraints/constraints.xdc
rename to fpga/constraints/constraints-vcu118.xdc
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index bf9402e1..551e4aca 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -1,4 +1,14 @@
 dst := IP
+# vcu118
+#export XILINX_PART := xcvu9p-flga2104-2L-e
+#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
+#export FREQ := 30
+
+# vcu108
+export XILINX_PART := xcvu095-ffva2104-2-e
+export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
+export board := vcu108
+
 
 all: FPGA
 
@@ -6,7 +16,7 @@ FPGA: IP
 	vivado -mode batch -source wally.tcl 2>&1 | tee wally.log
 
 IP: $(dst)/xlnx_proc_sys_reset.log \
-	$(dst)/xlnx_ddr4.log \
+	$(dst)/xlnx_ddr4-$(board).log \
 	$(dst)/xlnx_axi_clock_converter.log \
 	 $(dst)/xlnx_ahblite_axi_bridge.log
 
diff --git a/fpga/generator/dcache-miss-evict-dirty-deadlock.tsm b/fpga/generator/debug/dcache-miss-evict-dirty-deadlock.tsm
similarity index 100%
rename from fpga/generator/dcache-miss-evict-dirty-deadlock.tsm
rename to fpga/generator/debug/dcache-miss-evict-dirty-deadlock.tsm
diff --git a/fpga/generator/load-deadlock.tsm b/fpga/generator/debug/load-deadlock.tsm
similarity index 100%
rename from fpga/generator/load-deadlock.tsm
rename to fpga/generator/debug/load-deadlock.tsm
diff --git a/fpga/generator/debug/miss-fetch-deadlock.tsm b/fpga/generator/debug/miss-fetch-deadlock.tsm
new file mode 100644
index 00000000..63f985d6
--- /dev/null
+++ b/fpga/generator/debug/miss-fetch-deadlock.tsm
@@ -0,0 +1,37 @@
+##################################################
+#
+# For info on creating trigger state machines:
+#   1) In the main Vivado menu bar, select
+#      Window > Language Templates
+#   2) In the Templates window, select
+#      Debug > Trigger State Machine
+#   3) Refer to the entry 'Info' for an overview
+#      of the trigger state machine language.
+#
+# More information can be found in this document:
+#
+#   Vivado Design Suite User Guide: Programming
+#   and Debugging (UG908)
+#
+##################################################
+state state_reset:
+    if(wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState == 4'h1) then
+        reset_counter $counter0;
+        goto state_begin_count;
+        #goto state_trigger;
+    else
+        goto state_reset;
+    endif
+    
+state state_begin_count:
+    if($counter0 == 16'h0164) then
+        goto state_trigger;
+    elseif(wallypipelinedsoc/core/lsu/bus.dcache.dcache/cachefsm/CurrState == 4'h1) then
+        increment_counter $counter0;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_trigger:
+    trigger;
diff --git a/fpga/generator/trigger.tsm b/fpga/generator/debug/trigger.tsm
similarity index 100%
rename from fpga/generator/trigger.tsm
rename to fpga/generator/debug/trigger.tsm
diff --git a/fpga/generator/debug/uart-stuck.tsm b/fpga/generator/debug/uart-stuck.tsm
new file mode 100644
index 00000000..2670459b
--- /dev/null
+++ b/fpga/generator/debug/uart-stuck.tsm
@@ -0,0 +1,49 @@
+##################################################
+#
+# For info on creating trigger state machines:
+#   1) In the main Vivado menu bar, select
+#      Window > Language Templates
+#   2) In the Templates window, select
+#      Debug > Trigger State Machine
+#   3) Refer to the entry 'Info' for an overview
+#      of the trigger state machine language.
+#
+# More information can be found in this document:
+#
+#   Vivado Design Suite User Guide: Programming
+#   and Debugging (UG908)
+#
+##################################################
+state state_reset:
+    if(wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b1) then
+        reset_counter $counter0;
+        reset_counter $counter1;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_begin_count:
+    if(wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b0) then
+        reset_counter $counter0;
+        reset_counter $counter1;	
+        goto state_reset;
+    elseif($counter0 == 16'hFFFF && wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b1) then
+        goto state_count1;
+       else
+     	  increment_counter $counter0;
+          goto state_begin_count;
+       #endif
+    endif
+
+state state_count1:
+    if($counter1 == 16'h000F && wallypipelinedsoc/uncore.uncore/uart.uart/INTR == 1'b1) then
+           goto state_trigger;
+    else
+       increment_counter $counter1;
+       reset_counter $counter0;
+       goto state_begin_count;
+    endif
+    
+state state_trigger:
+    trigger;
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 60666077..6afa9e66 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -1,7 +1,8 @@
 # start by reading in all the IP blocks generated by vivado
 
-set partNumber xcvu9p-flga2104-2L-e
-set boardName  xilinx.com:vcu118:part0:2.4
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+set boardSubName [lindex [split ${boardName} :] 1]
 
 set ipName WallyFPGA
 
@@ -19,8 +20,9 @@ read_verilog  {../src/fpgaTop.v}
 
 set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset]
 
-add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
-set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints.xdc]
+
+add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
+set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints-$boardSubName.xdc]
 
 # define top level
 set_property top fpgaTop [current_fileset]
diff --git a/fpga/generator/xlnx_ahblite_axi_bridge.tcl b/fpga/generator/xlnx_ahblite_axi_bridge.tcl
index 317a62c0..6bd25296 100644
--- a/fpga/generator/xlnx_ahblite_axi_bridge.tcl
+++ b/fpga/generator/xlnx_ahblite_axi_bridge.tcl
@@ -1,10 +1,10 @@
 
-#set partNumber $::env(XILINX_PART)
-#set boardNmae $::env(XILINX_BOARD)
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
 
 # vcu118 board
-set partNumber xcvu9p-flga2104-2L-e
-set boardName  xilinx.com:vcu118:part0:2.4
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
 
 # kcu105 board
 #set partNumber  xcku040-ffva1156-2-e
diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/xlnx_axi_clock_converter.tcl
index 9e581c29..94303f3d 100644
--- a/fpga/generator/xlnx_axi_clock_converter.tcl
+++ b/fpga/generator/xlnx_axi_clock_converter.tcl
@@ -1,8 +1,8 @@
 
-#set partNumber $::env(XILINX_PART)
-#set boardNmae $::env(XILINX_BOARD)
-set partNumber xcvu9p-flga2104-2L-e
-set boardName  xilinx.com:vcu118:part0:2.4
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
 
 set ipName xlnx_axi_clock_converter
 
diff --git a/fpga/generator/xlnx_ddr4-vcu108.tcl b/fpga/generator/xlnx_ddr4-vcu108.tcl
new file mode 100644
index 00000000..71f8f06a
--- /dev/null
+++ b/fpga/generator/xlnx_ddr4-vcu108.tcl
@@ -0,0 +1,164 @@
+
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName xlnx_ddr4
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+# really just these two lines which change
+create_ip -name ddr4 -vendor xilinx.com -library ip -module_name $ipName
+set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
+			CONFIG.No_Controller {1} \
+			CONFIG.Phy_Only {Complete_Memory_Controller} \
+			CONFIG.C0.DDR4_PhyClockRatio {4:1} \
+			CONFIG.C0.DDR4_TimePeriod {1200} \
+			CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
+			CONFIG.C0.DDR4_BurstLength {8} \
+			CONFIG.C0.DDR4_BurstType {Sequential} \
+			CONFIG.C0.DDR4_CasLatency {13} \
+			CONFIG.C0.DDR4_CasWriteLatency {10} \
+			CONFIG.C0.DDR4_Slot {Single} \
+			CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
+			CONFIG.C0.DDR4_DataWidth {64} \
+			CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
+			CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} \
+			CONFIG.C0.DDR4_Ordering {Normal} \
+			CONFIG.C0.DDR4_Ecc {false} \
+			CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} \
+			CONFIG.C0.DDR4_AutoPrecharge {false} \
+			CONFIG.C0.DDR4_UserRefresh_ZQCS {false} \
+			CONFIG.C0.DDR4_AxiDataWidth {64} \
+			CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
+			CONFIG.C0.DDR4_AxiIDWidth {4} \
+			CONFIG.C0.DDR4_AxiAddressWidth {31} \
+			CONFIG.C0.DDR4_AxiNarrowBurst {false} \
+			CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
+			CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
+			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
+			CONFIG.Reference_Clock {Differential} \
+			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
+			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
+			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
+			CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT4_FREQ_HZ {None} \
+			CONFIG.Debug_Signal {Disable} \
+			CONFIG.MCS_DBG_EN {false} \
+			CONFIG.C0.DDR4_MCS_ECC {false} \
+			CONFIG.Simulation_Mode {BFM} \
+			CONFIG.Example_TG {SIMPLE_TG} \
+			CONFIG.C0.DDR4_SELF_REFRESH {false} \
+			CONFIG.RECONFIG_XSDB_SAVE_RESTORE {false} \
+			CONFIG.C0.DDR4_SAVE_RESTORE {false} \
+			CONFIG.C0.DDR4_RESTORE_CRC {false} \
+			CONFIG.C0.MIGRATION {false} \
+			CONFIG.AL_SEL {0} \
+			CONFIG.C0.ADDR_WIDTH {17} \
+			CONFIG.C0.BANK_GROUP_WIDTH {1} \
+			CONFIG.C0.CKE_WIDTH {1} \
+			CONFIG.C0.CK_WIDTH {1} \
+			CONFIG.C0.CS_WIDTH {1} \
+			CONFIG.C0.DDR4_ACT_SKEW {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_0 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_1 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_2 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_3 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_4 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_5 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_6 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_7 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_8 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_9 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_10 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_11 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_12 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_13 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_14 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_15 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_16 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_17 {0} \
+			CONFIG.C0.DDR4_AxiSelection {true} \
+			CONFIG.C0.DDR4_BA_SKEW_0 {0} \
+			CONFIG.C0.DDR4_BA_SKEW_1 {0} \
+			CONFIG.C0.DDR4_BG_SKEW_0 {0} \
+			CONFIG.C0.DDR4_BG_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_0 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_2 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_3 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_0 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_2 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_3 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_0 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_2 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_3 {0} \
+			CONFIG.C0.DDR4_Capacity {512} \
+			CONFIG.C0.DDR4_ChipSelect {true} \
+			CONFIG.C0.DDR4_Clamshell {false} \
+			CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
+			CONFIG.C0.DDR4_EN_PARITY {false} \
+			CONFIG.C0.DDR4_Enable_LVAUX {false} \
+			CONFIG.C0.DDR4_InputClockPeriod {3359} \
+			CONFIG.C0.DDR4_LR_SKEW_0 {0} \
+			CONFIG.C0.DDR4_LR_SKEW_1 {0} \
+			CONFIG.C0.DDR4_MemoryName {MainMemory} \
+			CONFIG.C0.DDR4_ODT_SKEW_0 {0} \
+			CONFIG.C0.DDR4_ODT_SKEW_1 {0} \
+			CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
+			CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
+			CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
+			CONFIG.C0.DDR4_PAR_SKEW {0} \
+			CONFIG.C0.DDR4_Specify_MandD {false} \
+			CONFIG.C0.DDR4_TREFI {0} \
+			CONFIG.C0.DDR4_TRFC {0} \
+			CONFIG.C0.DDR4_TRFC_DLR {0} \
+			CONFIG.C0.DDR4_TXPR {0} \
+			CONFIG.C0.DDR4_isCKEShared {false} \
+			CONFIG.C0.DDR4_isCustom {false} \
+			CONFIG.C0.DDR4_nCK_TREFI {0} \
+			CONFIG.C0.DDR4_nCK_TRFC {0} \
+			CONFIG.C0.DDR4_nCK_TRFC_DLR {0} \
+			CONFIG.C0.DDR4_nCK_TXPR {5} \
+			CONFIG.C0.LR_WIDTH {1} \
+			CONFIG.C0.ODT_WIDTH {1} \
+			CONFIG.C0.StackHeight {1} \
+			CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk1_300} \
+			CONFIG.C0_DDR4_ARESETN.INSERT_VIP {0} \
+			CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
+			CONFIG.C0_DDR4_CLOCK.INSERT_VIP {0} \
+			CONFIG.C0_DDR4_RESET.INSERT_VIP {0} \
+			CONFIG.C0_DDR4_S_AXI.INSERT_VIP {0} \
+			CONFIG.C0_SYS_CLK_I.INSERT_VIP {0} \
+			CONFIG.CLKOUT6 {0} \
+			CONFIG.DCI_Cascade {false} \
+			CONFIG.DIFF_TERM_SYSCLK {false} \
+			CONFIG.Default_Bank_Selections {false} \
+			CONFIG.EN_PP_4R_MIR {false} \
+			CONFIG.Enable_SysPorts {true} \
+			CONFIG.IOPowerReduction {OFF} \
+			CONFIG.IO_Power_Reduction {false} \
+			CONFIG.IS_FROM_PHY {1} \
+			CONFIG.PARTIAL_RECONFIG_FLOW_MIG {false} \
+			CONFIG.PING_PONG_PHY {1} \
+			CONFIG.RESET_BOARD_INTERFACE {reset} \
+			CONFIG.SET_DW_TO_40 {false} \
+			CONFIG.SYSTEM_RESET.INSERT_VIP {0} \
+			CONFIG.System_Clock {Differential} \
+			CONFIG.TIMING_3DS {false} \
+			CONFIG.TIMING_OP1 {false} \
+			CONFIG.TIMING_OP2 {false} \
+		       ] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1
diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/xlnx_ddr4-vcu118.tcl
new file mode 100644
index 00000000..cc5b61b2
--- /dev/null
+++ b/fpga/generator/xlnx_ddr4-vcu118.tcl
@@ -0,0 +1,165 @@
+
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
+
+set ipName xlnx_ddr4
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $boardName [current_project]
+
+# really just these two lines which change
+create_ip -name ddr4 -vendor xilinx.com -library ip -module_name $ipName
+set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
+			CONFIG.No_Controller {1} \
+			CONFIG.Phy_Only {Complete_Memory_Controller} \
+			CONFIG.C0.DDR4_PhyClockRatio {4:1} \
+			CONFIG.C0.DDR4_TimePeriod {1200} \
+			CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
+			CONFIG.C0.DDR4_BurstLength {8} \
+			CONFIG.C0.DDR4_BurstType {Sequential} \
+			CONFIG.C0.DDR4_CasLatency {13} \
+			CONFIG.C0.DDR4_CasWriteLatency {10} \
+			CONFIG.C0.DDR4_Slot {Single} \
+			CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
+			CONFIG.C0.DDR4_DataWidth {64} \
+			CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \
+			CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} \
+			CONFIG.C0.DDR4_Ordering {Normal} \
+			CONFIG.C0.DDR4_Ecc {false} \
+			CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} \
+			CONFIG.C0.DDR4_AutoPrecharge {false} \
+			CONFIG.C0.DDR4_UserRefresh_ZQCS {false} \
+			CONFIG.C0.DDR4_AxiDataWidth {64} \
+			CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
+			CONFIG.C0.DDR4_AxiIDWidth {4} \
+			CONFIG.C0.DDR4_AxiAddressWidth {31} \
+			CONFIG.C0.DDR4_AxiNarrowBurst {false} \
+			CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
+			CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
+			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
+			CONFIG.Reference_Clock {Differential} \
+			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {30} \
+			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
+			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
+			CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
+			CONFIG.ADDN_UI_CLKOUT4_FREQ_HZ {None} \
+			CONFIG.Debug_Signal {Disable} \
+			CONFIG.MCS_DBG_EN {false} \
+			CONFIG.C0.DDR4_MCS_ECC {false} \
+			CONFIG.Simulation_Mode {BFM} \
+			CONFIG.Example_TG {SIMPLE_TG} \
+			CONFIG.C0.DDR4_SELF_REFRESH {false} \
+			CONFIG.RECONFIG_XSDB_SAVE_RESTORE {false} \
+			CONFIG.C0.DDR4_SAVE_RESTORE {false} \
+			CONFIG.C0.DDR4_RESTORE_CRC {false} \
+			CONFIG.C0.MIGRATION {false} \
+			CONFIG.AL_SEL {0} \
+			CONFIG.C0.ADDR_WIDTH {17} \
+			CONFIG.C0.BANK_GROUP_WIDTH {1} \
+			CONFIG.C0.CKE_WIDTH {1} \
+			CONFIG.C0.CK_WIDTH {1} \
+			CONFIG.C0.CS_WIDTH {1} \
+			CONFIG.C0.DDR4_ACT_SKEW {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_0 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_1 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_2 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_3 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_4 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_5 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_6 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_7 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_8 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_9 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_10 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_11 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_12 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_13 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_14 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_15 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_16 {0} \
+			CONFIG.C0.DDR4_ADDR_SKEW_17 {0} \
+			CONFIG.C0.DDR4_AxiSelection {true} \
+			CONFIG.C0.DDR4_BA_SKEW_0 {0} \
+			CONFIG.C0.DDR4_BA_SKEW_1 {0} \
+			CONFIG.C0.DDR4_BG_SKEW_0 {0} \
+			CONFIG.C0.DDR4_BG_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_0 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_2 {0} \
+			CONFIG.C0.DDR4_CKE_SKEW_3 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_0 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_2 {0} \
+			CONFIG.C0.DDR4_CK_SKEW_3 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_0 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_1 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_2 {0} \
+			CONFIG.C0.DDR4_CS_SKEW_3 {0} \
+			CONFIG.C0.DDR4_Capacity {512} \
+			CONFIG.C0.DDR4_ChipSelect {true} \
+			CONFIG.C0.DDR4_Clamshell {false} \
+			CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
+			CONFIG.C0.DDR4_EN_PARITY {false} \
+			CONFIG.C0.DDR4_Enable_LVAUX {false} \
+			CONFIG.C0.DDR4_InputClockPeriod {4000} \
+			CONFIG.C0.DDR4_LR_SKEW_0 {0} \
+			CONFIG.C0.DDR4_LR_SKEW_1 {0} \
+			CONFIG.C0.DDR4_MemoryName {MainMemory} \
+			CONFIG.C0.DDR4_ODT_SKEW_0 {0} \
+			CONFIG.C0.DDR4_ODT_SKEW_1 {0} \
+			CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
+			CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
+			CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
+			CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
+			CONFIG.C0.DDR4_PAR_SKEW {0} \
+			CONFIG.C0.DDR4_Specify_MandD {false} \
+			CONFIG.C0.DDR4_TREFI {0} \
+			CONFIG.C0.DDR4_TRFC {0} \
+			CONFIG.C0.DDR4_TRFC_DLR {0} \
+			CONFIG.C0.DDR4_TXPR {0} \
+			CONFIG.C0.DDR4_isCKEShared {false} \
+			CONFIG.C0.DDR4_isCustom {false} \
+			CONFIG.C0.DDR4_nCK_TREFI {0} \
+			CONFIG.C0.DDR4_nCK_TRFC {0} \
+			CONFIG.C0.DDR4_nCK_TRFC_DLR {0} \
+			CONFIG.C0.DDR4_nCK_TXPR {5} \
+			CONFIG.C0.LR_WIDTH {1} \
+			CONFIG.C0.ODT_WIDTH {1} \
+			CONFIG.C0.StackHeight {1} \
+			CONFIG.C0_CLOCK_BOARD_INTERFACE {default_250mhz_clk1} \
+			CONFIG.C0_DDR4_ARESETN.INSERT_VIP {0} \
+			CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
+			CONFIG.C0_DDR4_CLOCK.INSERT_VIP {0} \
+			CONFIG.C0_DDR4_RESET.INSERT_VIP {0} \
+			CONFIG.C0_DDR4_S_AXI.INSERT_VIP {0} \
+			CONFIG.C0_SYS_CLK_I.INSERT_VIP {0} \
+			CONFIG.CLKOUT6 {0} \
+			CONFIG.DCI_Cascade {false} \
+			CONFIG.DIFF_TERM_SYSCLK {false} \
+			CONFIG.Default_Bank_Selections {false} \
+			CONFIG.EN_PP_4R_MIR {false} \
+			CONFIG.Enable_SysPorts {true} \
+			CONFIG.IOPowerReduction {OFF} \
+			CONFIG.IO_Power_Reduction {false} \
+			CONFIG.IS_FROM_PHY {1} \
+			CONFIG.PARTIAL_RECONFIG_FLOW_MIG {false} \
+			CONFIG.PING_PONG_PHY {1} \
+			CONFIG.RESET_BOARD_INTERFACE {reset} \
+			CONFIG.SET_DW_TO_40 {false} \
+			CONFIG.SYSTEM_RESET.INSERT_VIP {0} \
+			CONFIG.System_Clock {Differential} \
+			CONFIG.TIMING_3DS {false} \
+			CONFIG.TIMING_OP1 {false} \
+			CONFIG.TIMING_OP2 {false} \
+		       ] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1
diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl
index dd9e4d31..c3aac1f7 100644
--- a/fpga/generator/xlnx_ddr4.tcl
+++ b/fpga/generator/xlnx_ddr4.tcl
@@ -1,8 +1,9 @@
 
 #set partNumber $::env(XILINX_PART)
 #set boardNmae $::env(XILINX_BOARD)
-set partNumber xcvu9p-flga2104-2L-e
-set boardName  xilinx.com:vcu118:part0:2.4
+set partNumber xcvu095-ffva2104-2-e
+set boardName  xilinx.com:vcu108:part0:1.2
+
 
 set ipName xlnx_ddr4
 
@@ -41,7 +42,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {30} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
@@ -106,7 +107,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
 			CONFIG.C0.DDR4_EN_PARITY {false} \
 			CONFIG.C0.DDR4_Enable_LVAUX {false} \
-			CONFIG.C0.DDR4_InputClockPeriod {4000} \
+			CONFIG.C0.DDR4_InputClockPeriod {3359} \
 			CONFIG.C0.DDR4_LR_SKEW_0 {0} \
 			CONFIG.C0.DDR4_LR_SKEW_1 {0} \
 			CONFIG.C0.DDR4_MemoryName {MainMemory} \
@@ -115,7 +116,6 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
 			CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
 			CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
-			CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
 			CONFIG.C0.DDR4_PAR_SKEW {0} \
 			CONFIG.C0.DDR4_Specify_MandD {false} \
 			CONFIG.C0.DDR4_TREFI {0} \
@@ -131,7 +131,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.LR_WIDTH {1} \
 			CONFIG.C0.ODT_WIDTH {1} \
 			CONFIG.C0.StackHeight {1} \
-			CONFIG.C0_CLOCK_BOARD_INTERFACE {default_250mhz_clk1} \
+			CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk1_300} \
 			CONFIG.C0_DDR4_ARESETN.INSERT_VIP {0} \
 			CONFIG.C0_DDR4_BOARD_INTERFACE {Custom} \
 			CONFIG.C0_DDR4_CLOCK.INSERT_VIP {0} \
diff --git a/fpga/generator/xlnx_proc_sys_reset.tcl b/fpga/generator/xlnx_proc_sys_reset.tcl
index 61a5655c..c7674c7e 100644
--- a/fpga/generator/xlnx_proc_sys_reset.tcl
+++ b/fpga/generator/xlnx_proc_sys_reset.tcl
@@ -1,8 +1,8 @@
 
-#set partNumber $::env(XILINX_PART)
-#set boardNmae $::env(XILINX_BOARD)
-set partNumber xcvu9p-flga2104-2L-e
-set boardName  xilinx.com:vcu118:part0:2.4
+set partNumber $::env(XILINX_PART)
+set boardName $::env(XILINX_BOARD)
+#set partNumber xcvu9p-flga2104-2L-e
+#set boardName  xilinx.com:vcu118:part0:2.4
 
 set ipName xlnx_proc_sys_reset
 
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv
index ddc5e382..ac063840 100644
--- a/pipelined/src/uncore/uartPC16550D.sv
+++ b/pipelined/src/uncore/uartPC16550D.sv
@@ -155,6 +155,7 @@ module uartPC16550D(
 		//DLL <= #1 8'd11; // 10 Mhz
 		//DLL <= #1 8'd33; // 30 Mhz
 		DLL <= #1 8'd8; // 30 Mhz 230400
+		DLL <= #1 8'd24; // 22 Mhz 57600
 		DLM <= #1 8'b0;
       end else begin
 		DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
@@ -178,7 +179,7 @@ module uartPC16550D(
 		  // freq /baud / 16 = div
           //3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
 		  //3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in
-		      3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in 		  
+		      3'b000: if (DLAB) DLL <= #1 8'd24; //else TXHR <= #1 Din; // TX handled in 		  
           3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
           3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
           3'b011: LCR <= #1 Din;