From 14f9f41d2db6f9f2236a6a082ff5646046d4c40d Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 12 May 2022 20:45:45 +0000 Subject: [PATCH] Partitioned privileged pipeline registers into module --- addins/embench-iot | 2 +- addins/riscv-arch-test | 2 +- addins/riscv-dv | 2 +- addins/riscv-tests | 2 +- pipelined/src/ppa/ppa.sv | 6 +-- pipelined/src/privileged/privileged.sv | 25 ++++------ pipelined/src/privileged/privpiperegs.sv | 58 ++++++++++++++++++++++++ pipelined/testbench/testbench.sv | 2 +- 8 files changed, 75 insertions(+), 24 deletions(-) create mode 100644 pipelined/src/privileged/privpiperegs.sv diff --git a/addins/embench-iot b/addins/embench-iot index 261a65e0..2d2aaa7b 160000 --- a/addins/embench-iot +++ b/addins/embench-iot @@ -1 +1 @@ -Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9 +Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3 diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 307c77b2..effd553a 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 +Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f diff --git a/addins/riscv-dv b/addins/riscv-dv index a7e27bc0..cb4295f9 160000 --- a/addins/riscv-dv +++ b/addins/riscv-dv @@ -1 +1 @@ -Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172 +Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071 diff --git a/addins/riscv-tests b/addins/riscv-tests index cf04274f..3e2bf06b 160000 --- a/addins/riscv-tests +++ b/addins/riscv-tests @@ -1 +1 @@ -Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7 +Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94 diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv index 1ce9b449..083c76bf 100644 --- a/pipelined/src/ppa/ppa.sv +++ b/pipelined/src/ppa/ppa.sv @@ -264,9 +264,9 @@ module ppa_prioriyencoder #(parameter N = 8) ( end endmodule -module ppa_decoder ( - input logic [$clog2(N)-1:0] a, - output logic [N-1:0] y); +module ppa_decoder #(parameter WIDTH = 8) ( + input logic [$clog2(WIDTH)-1:0] a, + output logic [WIDTH-1:0] y); always_comb begin y = 0; y[a] = 1; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 548aa031..a0ea3ef6 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -88,10 +88,10 @@ module privileged ( logic sretM, mretM, sfencevmaM; logic IllegalCSRAccessM; - logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; + logic IllegalIEUInstrFaultM; logic IllegalFPUInstrM; - logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM; - logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; + logic InstrPageFaultM; + logic InstrAccessFaultM; logic IllegalInstrFaultM; logic MTrapM, STrapM; @@ -149,16 +149,11 @@ module privileged ( .CSRReadValW, .IllegalCSRAccessM, .BigEndianM); - // pipeline fault signals - flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, - {InstrPageFaultF, InstrAccessFaultF}, - {InstrPageFaultD, InstrAccessFaultD}); - flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE, - {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, // ** vs IllegalInstrFaultInD - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}); - flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, - {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); + privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, + .IllegalFPUInstrE, + .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM, .IllegalFPUInstrM); + trap trap(.reset, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, @@ -169,9 +164,7 @@ module privileged ( .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, - .PCM, - .IEUAdrM, - .InstrM, + .PCM, .IEUAdrM, .InstrM, .InstrValidM, .CommittedM, .TrapM, .MTrapM, .STrapM, .RetM, .InterruptM, .IntPendingM, diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv new file mode 100644 index 00000000..db1a7722 --- /dev/null +++ b/pipelined/src/privileged/privpiperegs.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// privpiperegs.sv +// +// Written: David_Harris@hmc.edu 12 May 2022 +// Modified: +// +// Purpose: Pipeline registers for early exceptions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module privpiperegs ( + input logic clk, reset, + input logic StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + input logic InstrPageFaultF, InstrAccessFaultF, + input logic IllegalIEUInstrFaultD, IllegalFPUInstrD, + output logic IllegalFPUInstrE, + output logic InstrPageFaultM, InstrAccessFaultM, + output logic IllegalIEUInstrFaultM, IllegalFPUInstrM +); + + logic InstrPageFaultD, InstrAccessFaultD; + logic InstrPageFaultE, InstrAccessFaultE; + logic IllegalIEUInstrFaultE; + + // pipeline fault signals + flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, + {InstrPageFaultF, InstrAccessFaultF}, + {InstrPageFaultD, InstrAccessFaultD}); + flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE, + {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}); + flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, + {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); +endmodule \ No newline at end of file diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index bf4903e5..d070aa3f 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -208,7 +208,7 @@ logic [3:0] dummy; always @(negedge clk) begin if (TEST == "coremark") - if (dut.core.priv.priv.ecallM) begin + if (dut.core.priv.priv.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end