From 1404d1c248ff6a92ef2d44b0e8352d8f27c1a279 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 22 Aug 2022 08:41:23 +0000
Subject: [PATCH] moved CSA to generic

---
 pipelined/src/fpu/srt.sv     | 23 ------------------
 pipelined/src/generic/csa.sv | 45 ++++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+), 23 deletions(-)
 create mode 100644 pipelined/src/generic/csa.sv

diff --git a/pipelined/src/fpu/srt.sv b/pipelined/src/fpu/srt.sv
index 27519c95..72f84b2d 100644
--- a/pipelined/src/fpu/srt.sv
+++ b/pipelined/src/fpu/srt.sv
@@ -242,28 +242,5 @@ module divinteration (
 endmodule
 
 
-/////////
-// csa //
-/////////
-module csa #(parameter N=69) (
-  input  logic [N-1:0] in1, in2, in3, 
-  input  logic         cin, 
-  output logic [N-1:0] out1, out2
-);
-
-  // This block adds in1, in2, in3, and cin to produce 
-  // a result out1 / out2 in carry-save redundant form.
-  // cin is just added to the least significant bit and
-  // is Startuired to handle adding a negative divisor.
-  // Fortunately, the carry (out2) is shifted left by one
-  // bit, leaving room in the least significant bit to 
-  // insert cin.
-
-  assign out1 = in1 ^ in2 ^ in3;
-  assign out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) | 
-		    (in2[N-2:0] & in3[N-2:0]), cin};
-endmodule
-
-
 
 
diff --git a/pipelined/src/generic/csa.sv b/pipelined/src/generic/csa.sv
new file mode 100644
index 00000000..9251b346
--- /dev/null
+++ b/pipelined/src/generic/csa.sv
@@ -0,0 +1,45 @@
+///////////////////////////////////////////
+// csa.sv
+//
+// Written: Katherine Parry and David_Harris@hmc.edu 21 August 2022
+// Modified: 
+//
+// Purpose: 3:2 carry-save adder
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module csa #(parameter N=16) (
+  input  logic [N-1:0] x, y, z, 
+  input  logic         cin, 
+  output logic [N-1:0] s, c
+);
+
+  // This block adds x, y, z, and cin to produce 
+  // a result s / c in carry-save redundant form.
+  // cin is just added to the least significant bit
+  // s + c = x + y + z + cin
+ 
+  assign s = x ^ y ^ z;
+  assign c = {x[N-2:0] & (y[N-2:0] | z[N-2:0]) | 
+		    (y[N-2:0] & z[N-2:0]), cin};
+endmodule