From 13cf7c0934077100e04a962a9bcf0738457dc3c4 Mon Sep 17 00:00:00 2001 From: bbracker Date: Fri, 25 Jun 2021 09:28:52 -0400 Subject: [PATCH] linux testbench now ignores HWRITE glitches caused by flush glitches --- wally-pipelined/regression/wave-dos/linux-waves.do | 1 + wally-pipelined/testbench/testbench-linux.sv | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/regression/wave-dos/linux-waves.do b/wally-pipelined/regression/wave-dos/linux-waves.do index b3727644..63623891 100644 --- a/wally-pipelined/regression/wave-dos/linux-waves.do +++ b/wally-pipelined/regression/wave-dos/linux-waves.do @@ -4,6 +4,7 @@ view wave add wave -divider add wave /testbench/clk add wave /testbench/reset +add wave -dec /testbench/instrs add wave -divider Stalls_and_Flushes add wave /testbench/dut/hart/StallF diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index b87174b9..6676d1a7 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ module testbench(); - parameter waveOnICount = 2514000; // # of instructions at which to turn on waves in graphical sim + parameter waveOnICount = 2657000; // # of instructions at which to turn on waves in graphical sim /////////////////////////////////////////////////////////////////////////////// @@ -491,7 +491,7 @@ module testbench(); //always @(HWDATA or HADDR or HSIZE or HWRITE) begin always @(negedge HWRITE) begin //#1; - if ($time != 0) begin + if (($time != 0) && ~dut.hart.hzu.FlushM) begin if($feof(data_file_memW)) begin $display("no more memW data to read"); `ERROR