diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index e4b75a08..0f426d11 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -136,7 +136,7 @@ add wave /testbench_busybear/InstrMName #add wave -hex /testbench_busybear/dut/hart/dmem/AdrM #add wave -hex /testbench_busybear/dut/hart/dmem/WriteDataM #add wave -divider -add wave -hex /testbench_busybear/dut/hart/ifu/PCW +add wave -hex /testbench_busybear/PCW ##add wave -hex /testbench_busybear/dut/hart/ifu/InstrW add wave /testbench_busybear/InstrWName #add wave /testbench_busybear/dut/hart/ieu/dp/RegWriteW diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index ea63e2ae..5a309b78 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -69,8 +69,8 @@ add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/InstrM add wave /testbench/InstrMName add wave -divider Write -add wave -hex /testbench/dut/hart/ifu/PCW -add wave -hex /testbench/dut/hart/ifu/InstrW +add wave -hex /testbench/PCW +add wave -hex /testbench/InstrW add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcAE #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE @@ -81,7 +81,7 @@ add wave -divider Regfile_signals #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA #add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCW +#add wave -hex /testbench/PCW #add wave /testbench/InstrWName #add wave /testbench/dut/hart/ieu/dp/RegWriteW #add wave -hex /testbench/dut/hart/ieu/dp/ResultW diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 63c2e64f..9318c494 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -69,8 +69,8 @@ add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/InstrM add wave /testbench/InstrMName add wave -divider Write -add wave -hex /testbench/dut/hart/ifu/PCW -add wave -hex /testbench/dut/hart/ifu/InstrW +add wave -hex /testbench/PCW +add wave -hex /testbench/InstrW add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcAE #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE @@ -81,7 +81,7 @@ add wave -divider Regfile_signals #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA #add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCW +#add wave -hex /testbench/PCW #add wave /testbench/InstrWName #add wave /testbench/dut/hart/ieu/dp/RegWriteW #add wave -hex /testbench/dut/hart/ieu/dp/ResultW diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do index a6a0747b..cd2b453b 100644 --- a/wally-pipelined/regression/wave-all.do +++ b/wally-pipelined/regression/wave-all.do @@ -45,7 +45,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA add wave -noupdate -divider -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW +add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate /testbench/InstrWName add wave -noupdate /testbench/dut/hart/ieu/dp/RegWriteW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW @@ -219,7 +219,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/IllegalCompInstrD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlusUpperF add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCPlus2or4F add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCD -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCW +add wave -noupdate -radix hexadecimal /testbench/PCW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ifu/PCLinkM diff --git a/wally-pipelined/regression/wave-dos/ahb-waves.do b/wally-pipelined/regression/wave-dos/ahb-waves.do index f24def65..5101c757 100644 --- a/wally-pipelined/regression/wave-dos/ahb-waves.do +++ b/wally-pipelined/regression/wave-dos/ahb-waves.do @@ -55,8 +55,8 @@ add wave -hex /testbench/dut/hart/ebu/CaptureDataM add wave -hex /testbench/dut/hart/ebu/InstrStall add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCW -add wave -hex /testbench/dut/hart/ifu/InstrW +add wave -hex /testbench/PCW +add wave -hex /testbench/InstrW add wave /testbench/InstrWName add wave /testbench/dut/hart/ieu/dp/RegWriteW add wave -hex /testbench/dut/hart/ebu/ReadDataW diff --git a/wally-pipelined/regression/wave-dos/default-waves.do b/wally-pipelined/regression/wave-dos/default-waves.do index bdc9bf45..4b921435 100644 --- a/wally-pipelined/regression/wave-dos/default-waves.do +++ b/wally-pipelined/regression/wave-dos/default-waves.do @@ -40,8 +40,8 @@ add wave /testbench/dut/uncore/dtim/memwrite add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA add wave -divider -add wave -hex /testbench/dut/hart/ifu/PCW -add wave -hex /testbench/dut/hart/ifu/InstrW +add wave -hex /testbench/PCW +add wave -hex /testbench/InstrW add wave /testbench/InstrWName add wave /testbench/dut/hart/ieu/dp/RegWriteW add wave -hex /testbench/dut/hart/ieu/dp/ResultW diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 379c7ab4..c3772967 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -125,7 +125,7 @@ add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW +add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr add wave -noupdate -group {function radix debug} -radix unsigned /testbench/functionRadix/function_radix/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/reset diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index eb65e167..c869aa2c 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -71,9 +71,9 @@ module ifu ( logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic PrivilegedChangePCM; logic IllegalCompInstrD; - logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkM; + logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCLinkD, PCLinkM; logic CompressedF; - logic [31:0] InstrF, InstrRawD, InstrE, InstrW; + logic [31:0] InstrF, InstrRawD, InstrE; logic [31:0] nop = 32'h00000013; // instruction for NOP // *** temporary hack until walker is hooked up -- Thomas F @@ -196,10 +196,10 @@ module ifu ( flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE); flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM); - flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later + // flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later + // flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later flopenrc #(4) InstrClassRegE(.clk(clk), .reset(reset), diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 6f957efa..ff23d051 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -143,6 +143,9 @@ module testbench_busybear(); logic [63:0] pcExpected; logic [63:0] regExpected; integer regNumExpected; + logic [`XLEN-1:0] PCW; + + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); genvar i; generate @@ -349,8 +352,8 @@ module testbench_busybear(); string PCtextW, PCtext2W; logic [31:0] InstrWExpected; logic [63:0] PCWExpected; - always @(dut.hart.ifu.PCW or dut.hart.ieu.InstrValidW) begin - if(dut.hart.ieu.InstrValidW && dut.hart.ifu.PCW != 0) begin + always @(PCW or dut.hart.ieu.InstrValidW) begin + if(dut.hart.ieu.InstrValidW && PCW != 0) begin if($feof(data_file_PCW)) begin $display("no more PC data to read"); `ERROR @@ -363,8 +366,8 @@ module testbench_busybear(); scan_file_PCW = $fscanf(data_file_PCW, "%x\n", InstrWExpected); // then expected PC value scan_file_PCW = $fscanf(data_file_PCW, "%x\n", PCWExpected); - if(~equal(dut.hart.ifu.PCW,PCWExpected,2)) begin - $display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, dut.hart.ifu.PCW, PCWExpected); + if(~equal(PCW,PCWExpected,2)) begin + $display("%0t ps, instr %0d: PCW does not equal PCW expected: %x, %x", $time, instrs, PCW, PCWExpected); `ERROR end //if(it.InstrW != InstrWExpected) begin @@ -505,6 +508,7 @@ module testbench_busybear(); // Track names of instructions string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.hazard.StallW, dut.hart.hazard.FlushW ? nop : dut.hart.ifu.InstrM, InstrW); instrNameDecTB dec(dut.hart.ifu.InstrF, InstrFName); instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index fbec9f46..44c31f71 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -60,12 +60,18 @@ module testbench(); assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); // Track names of instructions + logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.hazard.StallW, dut.hart.hazard.FlushW ? nop : dut.hart.ifu.InstrM, InstrW); instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests + + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); + integer j; initial begin diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 0035450d..9018df09 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -59,12 +59,20 @@ module testbench(); assign HRESPEXT = 0; assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); + + logic [31:0] InstrW; + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.hazard.StallW, dut.hart.hazard.FlushW ? nop : dut.hart.ifu.InstrM, InstrW); + // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); + // initialize tests integer j; initial diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 2f6f0efb..fd5eea64 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -38,7 +38,7 @@ module testbench(); logic [`XLEN-1:0] signature[0:10000]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - //logic [31:0] InstrW; + logic [31:0] InstrW; logic [`XLEN-1:0] meminit; string tests64a[] = '{ "rv64a/WALLY-AMO", "2110", @@ -332,8 +332,10 @@ string tests32i[] = { logic [1:0] HTRANS; logic HMASTLOCK; logic HCLK, HRESETn; - + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~dut.hart.hazard.StallW, dut.hart.ifu.PCM, PCW); + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.hazard.StallW, dut.hart.hazard.FlushW ? nop : dut.hart.ifu.InstrM, InstrW); // pick tests based on modes supported initial if (`XLEN == 64) begin // RV64 @@ -372,7 +374,7 @@ string tests32i[] = { // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests diff --git a/wally-pipelined/testbench/testbench-peripherals.sv b/wally-pipelined/testbench/testbench-peripherals.sv index ba4b94fa..3a4ea3b1 100644 --- a/wally-pipelined/testbench/testbench-peripherals.sv +++ b/wally-pipelined/testbench/testbench-peripherals.sv @@ -73,13 +73,15 @@ module testbench(); assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); - + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.hazard.StallW, dut.hart.hazard.FlushW ? nop : dut.hart.ifu.InstrM, InstrW); // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, InstrW, InstrDName, InstrEName, InstrMName, InstrWName); + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); // initialize tests initial begin diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv index 99960448..6785f702 100644 --- a/wally-pipelined/testbench/testbench-privileged.sv +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -73,13 +73,15 @@ module testbench(); assign HRDATAEXT = 0; wallypipelinedsoc dut(.*); - + flopenr #(32) InstrWReg(clk, reset, ~dut.hart.hazard.StallW, dut.hart.hazard.FlushW ? nop : dut.hart.ifu.InstrM, InstrW); // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, InstrW, InstrDName, InstrEName, InstrMName, InstrWName); + logic [`XLEN-1:0] PCW; + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.hart.ifu.PCM, PCW); // initialize tests initial begin