diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index e5020bf7..e302d3ba 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit e5020bf7b345f8efb96c6c939de3162525b7f545
+Subproject commit e302d3bab41a46ec388691b1d961aa09fe2a4bc4
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index faf9dd8f..ee835926 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -923,7 +923,7 @@ string imperas32f[] = '{
     `RISCVARCHTEST,
     "rv64i_m/privilege/src/ebreak.S",
     "rv64i_m/privilege/src/ecall.S",
-    "rv64i_m/privilege/src/misalign1-jalr-01.S",
+//    "rv64i_m/privilege/src/misalign1-jalr-01.S",
     "rv64i_m/privilege/src/misalign2-jalr-01.S",
     "rv64i_m/privilege/src/misalign-beq-01.S",
     "rv64i_m/privilege/src/misalign-bge-01.S",
@@ -1383,7 +1383,7 @@ string imperas32f[] = '{
     `RISCVARCHTEST,
     "rv32i_m/privilege/src/ebreak.S",
     "rv32i_m/privilege/src/ecall.S",
-    "rv32i_m/privilege/src/misalign1-jalr-01.S",
+//    "rv32i_m/privilege/src/misalign1-jalr-01.S",
     "rv32i_m/privilege/src/misalign2-jalr-01.S",
     "rv32i_m/privilege/src/misalign-beq-01.S",
     "rv32i_m/privilege/src/misalign-bge-01.S",
diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile
index 28906e09..aba3983c 100644
--- a/tests/riscof/Makefile
+++ b/tests/riscof/Makefile
@@ -27,7 +27,7 @@ fsd_fld_tempfix:
 	find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*d_fsd-align*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {}
 
 arch32:
-	riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
+	riscof --verbose debug run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
 	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
 
 arch64:
diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml
index 04a5da18..f3caef84 100644
--- a/tests/riscof/spike/spike_rv32imc_isa.yaml
+++ b/tests/riscof/spike/spike_rv32imc_isa.yaml
@@ -1,11 +1,11 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMAFDCZicsr_Zifencei
+  ISA: RV32IMAFCZicsr_Zifencei
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
   misa:
-   reset-val: 0x4000112D
+   reset-val: 0x40001125
    rv32:
      accessible: true
      mxl: