From 11b0607e63c8ab4c096a29cb907b1f4122b50408 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 23 Oct 2021 09:06:21 -0700
Subject: [PATCH] Lint cleanup

---
 wally-pipelined/src/cache/cachereplacementpolicy.sv | 4 +++-
 wally-pipelined/src/fpu/fma.sv                      | 2 --
 wally-pipelined/src/mmu/tlbcontrol.sv               | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv
index 5a952129..8ba0c185 100644
--- a/wally-pipelined/src/cache/cachereplacementpolicy.sv
+++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv
@@ -43,10 +43,11 @@ module cachereplacementpolicy
   logic [NUMWAYS-2:0] 				BlockReplacementBits;
   logic [NUMWAYS-2:0] 				NewReplacement;
 
+  /* verilator lint_off BLKLOOPINIT */
   always_ff @(posedge clk, posedge reset) begin
     if (reset) begin
       for(int index = 0; index < NUMLINES; index++)
-	      ReplacementBits[index] = '0;
+	      ReplacementBits[index] <= '0;
     end else begin
       BlockReplacementBits <= ReplacementBits[RAdr];
       if (LRUWriteEn) begin
@@ -54,6 +55,7 @@ module cachereplacementpolicy
       end
     end
   end
+  /* verilator lint_on BLKLOOPINIT */
 
 
   genvar 		      index;
diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv
index 1f196a31..d5be1120 100644
--- a/wally-pipelined/src/fpu/fma.sv
+++ b/wally-pipelined/src/fpu/fma.sv
@@ -804,7 +804,6 @@ module fmaflags(
     output logic                Invalid, Overflow, Underflow, // flags used to select the result
     output logic [4:0]          FMAFlgM // FMA flags
 );
-    logic [`NE+1:0]     MaxExp;     // maximum value of the exponent
     logic               SigNaN;     // is an input a signaling NaN
     logic               UnderflowFlag, Inexact; // flags
 
@@ -819,7 +818,6 @@ module fmaflags(
     //   2) Inf - Inf (unless x or y is NaN)
     //   3) 0 * Inf
 
-    // assign MaxExp = FmtM ? {`NE{1'b1}} : {8{1'b1}};
     assign SigNaN = XSNaNM | YSNaNM | ZSNaNM;
     assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM);  
    
diff --git a/wally-pipelined/src/mmu/tlbcontrol.sv b/wally-pipelined/src/mmu/tlbcontrol.sv
index 109a8c43..2f8c5afa 100644
--- a/wally-pipelined/src/mmu/tlbcontrol.sv
+++ b/wally-pipelined/src/mmu/tlbcontrol.sv
@@ -89,7 +89,7 @@ module tlbcontrol #(parameter ITLB = 0) (
  
   // Check whether the access is allowed, page faulting if not.
   generate
-    if (ITLB == 1) begin
+    if (ITLB == 1) begin // Instruction TLB fault checking
       logic ImproperPrivilege;
 
       // User mode may only execute user mode pages, and supervisor mode may
@@ -99,7 +99,7 @@ module tlbcontrol #(parameter ITLB = 0) (
       // fault for software handling if access bit is off
       assign DAPageFault = ~PTE_A;
       assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAPageFault || UpperBitsUnequalPageFault);
-    end else begin
+    end else begin // Data TLB fault checking
       logic ImproperPrivilege, InvalidRead, InvalidWrite;
 
       // User mode may only load/store from user mode pages, and supervisor mode