diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv
index 9e05abcc..8ebf00d9 100644
--- a/wally-pipelined/src/uncore/uartPC16550D.sv
+++ b/wally-pipelined/src/uncore/uartPC16550D.sv
@@ -71,7 +71,7 @@ module uartPC16550D(
   // Baud and rx/tx timing
   logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
   logic [16+`UART_PRESCALE-1:0] baudcount;
-  logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
+  logic [3:0] 			rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
   logic [3:0] rxbitsreceived, txbitssent;
   statetype rxstate, txstate;
 
@@ -133,7 +133,7 @@ module uartPC16550D(
     if (~HRESETn) begin // Table 3 Reset Configuration
       IER <= #1 4'b0;
       FCR <= #1 8'b0;
-      if (`QEMU) LCR <= #1 8'b11; else LCR <= #1 8'b0;
+      if (`QEMU) LCR <= #1 8'b0; else LCR <= #1 8'b11; // fpga only **** BUG
       MCR <= #1 5'b0;
       LSR <= #1 8'b01100000;
       MSR <= #1 4'b0;
@@ -256,7 +256,7 @@ module uartPC16550D(
 
   generate
     if(`QEMU)
-      assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b10);  // implies rxstate = UART_ACTIVE
+      assign rxcentered = rxbaudpulse & (rxoversampledcnt[1:0] == 2'b10);  // implies rxstate = UART_ACTIVE
     else
       assign rxcentered = rxbaudpulse & (rxoversampledcnt == 4'b1000);  // implies rxstate = UART_ACTIVE      
   endgenerate
@@ -382,7 +382,7 @@ module uartPC16550D(
   assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s)
   generate
     if (`QEMU)
-      assign txnextbit = txbaudpulse & (txoversampledcnt == 2'b00);  // implies txstate = UART_ACTIVE
+      assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00);  // implies txstate = UART_ACTIVE
     else
       assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000);  // implies txstate = UART_ACTIVE
   endgenerate