From 113258a0d0cb83d901768b985865112253222697 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Aug 2022 12:17:19 -0700 Subject: [PATCH] Cleaned up fcvt selection control to IEU and FPUIllegalInst signals --- pipelined/src/fpu/fctrl.sv | 25 +++++++++++------------ pipelined/src/fpu/fpu.sv | 13 ++++++------ pipelined/src/ieu/datapath.sv | 6 ++---- pipelined/src/ieu/ieu.sv | 8 +++----- pipelined/src/privileged/privdec.sv | 5 ++--- pipelined/src/privileged/privileged.sv | 9 +++----- pipelined/src/privileged/privpiperegs.sv | 17 ++++++++------- pipelined/src/wally/wallypipelinedcore.sv | 20 ++++++++++-------- 8 files changed, 47 insertions(+), 56 deletions(-) diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index aab6872e..36798321 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -41,7 +41,7 @@ module fctrl ( input logic [2:0] FRM_REGW, // rounding mode from CSR input logic [1:0] STATUS_FS, // is FPU enabled? input logic FDivBusyE, // is the divider busy - output logic IllegalFPUInstrD, IllegalFPUInstrM, // Is the instruction an illegal fpu instruction + output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction output logic FRegWriteM, FRegWriteW, // FP register write enable output logic [2:0] FrmM, // FP rounding mode output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format @@ -52,12 +52,13 @@ module fctrl ( output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit + output logic FCvtIntW, output logic [4:0] Adr1E, Adr2E, Adr3E // adresses of each input ); `define FCTRLW 11 logic [`FCTRLW-1:0] ControlsD; - logic IllegalFPUInstrE; + logic IllegalFPUInstrD, IllegalFPUInstrE; logic FRegWriteD; // FP register write enable logic DivStartD; // integer register write enable logic FWriteIntD; // integer register write enable @@ -257,23 +258,21 @@ module fctrl ( // 10 - xor sign // D/E pipleine register - flopenrc #(12+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, - {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD}, - {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE}); - flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, + flopenrc #(13+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, + {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, IllegalFPUInstrD}, + {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE}); + flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, {Adr1E, Adr2E, Adr3E}); flopenrc #(1) DEDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, DivStartD, DivStartE); - if(`FLEN>`XLEN) - flopenrc #(1) DEIllegalReg(clk, reset, FlushE, ~StallE, IllegalFPUInstrD, IllegalFPUInstrE); // E/M pipleine register - flopenrc #(12+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM, - {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE}, - {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM}); - if(`FLEN>`XLEN) - flopenrc #(1) EMIllegalReg(clk, reset, FlushM, ~StallM, IllegalFPUInstrE, IllegalFPUInstrM); + flopenrc #(13+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM, + {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE}, + {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM, IllegalFPUInstrM}); // M/W pipleine register flopenrc #(3) MWCtrlReg(clk, reset, FlushW, ~StallW, {FRegWriteM, FResSelM}, {FRegWriteW, FResSelW}); + + assign FCvtIntW = (FResSelW == 2'b01); endmodule diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index af26052e..57fd4aa1 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -47,9 +47,9 @@ module fpu ( output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) - output logic [1:0] FResSelW, // final result selection (to IEU) + output logic FCvtIntW, // select FCvtIntRes (to IEU) output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) - output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to privileged unit) + output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction (to privileged unit) output logic [4:0] SetFflagsM // FPU flags (to privileged unit) ); @@ -67,10 +67,9 @@ module fpu ( logic FWriteIntM; // Write to integer register logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component - logic [1:0] FResSelE, FResSelM; // Select one of the results that finish in the memory stage + logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input - logic IllegalFPUInstrM; logic XEnE, YEnE, ZEnE; logic YEnForwardE, ZEnForwardE; @@ -147,7 +146,7 @@ module fpu ( logic [`FLEN-1:0] AlignedSrcAE; // align SrcA to the floating point format logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed logic [`FLEN-1:0] BoxedOneE; // Zero value for Z for multiplication, with NaN boxing if needed - + // DECODE STAGE ////////////////////////////////////////////////////////////////////////////////////////// @@ -163,9 +162,9 @@ module fpu ( // calculate FP control signals fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .InstrD, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE, - .reset, .clk, .IllegalFPUInstrD, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE, + .reset, .clk, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE, .DivStartE, .FWriteIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE, - .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .Adr1E, .Adr2E, .Adr3E); + .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1E, .Adr2E, .Adr3E); // FP register file fregfile fregfile (.clk, .reset, .we4(FRegWriteW), diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 57150131..89ebd9b5 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -44,7 +44,6 @@ module datapath ( input logic ALUResultSrcE, input logic JumpE, input logic BranchSignedE, - input logic IllegalFPUInstrE, input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCLinkE, output logic [1:0] FlagsE, @@ -52,7 +51,7 @@ module datapath ( output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B // Memory stage signals input logic StallM, FlushM, - input logic FWriteIntM, + input logic FWriteIntM, FCvtIntW, input logic [`XLEN-1:0] FIntResM, output logic [`XLEN-1:0] SrcAM, output logic [`XLEN-1:0] WriteDataM, @@ -62,7 +61,6 @@ module datapath ( input logic SquashSCW, input logic [2:0] ResultSrcW, input logic [`XLEN-1:0] FCvtIntResW, - input logic [1:0] FResSelW, input logic [`XLEN-1:0] ReadDataW, // input logic [`XLEN-1:0] PCLinkW, input logic [`XLEN-1:0] CSRReadValW, MDUResultW, @@ -126,7 +124,7 @@ module datapath ( // floating point inputs: FIntResM comes from fclass, fcmp, fmv; FCvtIntResW comes from fcvt if (`F_SUPPORTED) begin:fpmux mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); - mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW); + mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW); end else begin:fpmux assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW; end diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 52080706..d7101b87 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -39,8 +39,7 @@ module ieu ( // Execute Stage interface input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCLinkE, - input logic FWriteIntE, - input logic IllegalFPUInstrE, + input logic FWriteIntE, FCvtIntW, output logic [`XLEN-1:0] IEUAdrE, output logic MDUE, W64E, output logic [2:0] Funct3E, @@ -60,7 +59,6 @@ module ieu ( // Writeback stage input logic [`XLEN-1:0] CSRReadValW, MDUResultW, - input logic [1:0] FResSelW, input logic [`XLEN-1:0] FCvtIntResW, output logic [4:0] RdW, input logic [`XLEN-1:0] ReadDataW, @@ -105,9 +103,9 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .IllegalFPUInstrE, + .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, - .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FResSelW, + .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index 367c9e82..a63bf982 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -43,7 +43,7 @@ module privdec ( output logic EcallFaultM, BreakpointFaultM, output logic sretM, mretM, wfiM, sfencevmaM); - logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM; + logic IllegalPrivilegedInstrM; logic WFITimeoutM; logic StallMQ; logic ebreakM, ecallM; @@ -92,7 +92,6 @@ module privdec ( // Fault on illegal instructions /////////////////////////////////////////// assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); - assign IllegalOrDisabledFPUInstrM = IllegalFPUInstrM | (STATUS_FS == 2'b00); - assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalOrDisabledFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | + assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | WFITimeoutM; endmodule diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index f9f8a99a..029ab2e5 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -52,7 +52,7 @@ module privileged ( input logic ICacheAccess, input logic PrivilegedM, input logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, - input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, + input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrM, input logic LoadMisalignedFaultM, input logic StoreAmoMisalignedFaultM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, @@ -69,7 +69,6 @@ module privileged ( input logic StoreAmoAccessFaultM, input logic SelHPTW, - output logic IllegalFPUInstrE, output logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] SATP_REGW, output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -88,7 +87,6 @@ module privileged ( logic sretM, mretM; logic IllegalCSRAccessM; logic IllegalIEUInstrFaultM; - logic IllegalFPUInstrM; logic InstrPageFaultM; logic InstrAccessFaultM; logic IllegalInstrFaultM; @@ -148,9 +146,8 @@ module privileged ( .IllegalCSRAccessM, .BigEndianM); privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, - .IllegalFPUInstrE, - .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM, .IllegalFPUInstrM); + .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, + .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM); trap trap(.reset, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv index db1a7722..541f0413 100644 --- a/pipelined/src/privileged/privpiperegs.sv +++ b/pipelined/src/privileged/privpiperegs.sv @@ -35,10 +35,9 @@ module privpiperegs ( input logic StallD, StallE, StallM, input logic FlushD, FlushE, FlushM, input logic InstrPageFaultF, InstrAccessFaultF, - input logic IllegalIEUInstrFaultD, IllegalFPUInstrD, - output logic IllegalFPUInstrE, + input logic IllegalIEUInstrFaultD, output logic InstrPageFaultM, InstrAccessFaultM, - output logic IllegalIEUInstrFaultM, IllegalFPUInstrM + output logic IllegalIEUInstrFaultM ); logic InstrPageFaultD, InstrAccessFaultD; @@ -49,10 +48,10 @@ module privpiperegs ( flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, {InstrPageFaultF, InstrAccessFaultF}, {InstrPageFaultD, InstrAccessFaultD}); - flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE, - {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}); - flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, - {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); + flopenrc #(3) faultregE(clk, reset, FlushE, ~StallE, + {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD}, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE}); + flopenrc #(3) faultregM(clk, reset, FlushM, ~StallM, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE}, + {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM}); endmodule \ No newline at end of file diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index f1af3429..cd71ee41 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -94,9 +94,10 @@ module wallypipelinedcore ( logic FWriteIntE; logic [`FLEN-1:0] FWriteDataM; logic [`XLEN-1:0] FIntResM; - logic [`XLEN-1:0] FCvtIntResW; + logic [`XLEN-1:0] FCvtIntResW; + logic FCvtIntW; logic FDivBusyE; - logic IllegalFPUInstrD, IllegalFPUInstrE; + logic IllegalFPUInstrM; logic FRegWriteM; logic FPUStallD; logic FpLoadStoreM; @@ -217,7 +218,7 @@ module wallypipelinedcore ( .IllegalBaseInstrFaultD, // Execute Stage interface - .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE, + .PCE, .PCLinkE, .FWriteIntE, .IEUAdrE, .MDUE, .W64E, .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B @@ -235,7 +236,7 @@ module wallypipelinedcore ( .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .FCvtIntResW, - .FResSelW, + .FCvtIntW, // hazards .StallD, .StallE, .StallM, .StallW, @@ -344,7 +345,7 @@ module wallypipelinedcore ( .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, - .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, + .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, @@ -354,7 +355,7 @@ module wallypipelinedcore ( // *** do these need to be split up into one for dmem and one for ifu? // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem? .InstrAccessFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, - .IllegalFPUInstrE, + .IllegalFPUInstrM, .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, @@ -400,17 +401,18 @@ module wallypipelinedcore ( .FWriteDataM, // Data to be written to memory .FIntResM, // data to be written to integer register .FCvtIntResW, // fp -> int conversion result to be stored in int register - .FResSelW, // fpu result selection + .FCvtIntW, // fpu result selection .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) - .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction + .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction .SetFflagsM // FPU flags (to privileged unit) ); // floating point unit end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low assign FStallD = 0; assign FWriteIntE = 0; assign FIntResM = 0; + assign FCvtIntW = 0; assign FDivBusyE = 0; - assign IllegalFPUInstrD = 1; + assign IllegalFPUInstrM = 1; assign SetFflagsM = 0; end endmodule