From 1018a106256078d227e0e403770d891655187e57 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Tue, 13 Apr 2021 11:27:12 -0500 Subject: [PATCH] Various code syntax changes to bring HDL to a synthesizable level --- .../{src => misc}/tlb_toy/tlb_testbench.sv | 0 .../{src => misc}/tlb_toy/tlb_toy.sv.OLD | 0 .../{src => misc}/tlb_toy/tlb_toy.tv | 0 wally-pipelined/src/cache/dmapped.sv | 16 +-- wally-pipelined/src/cache/line.sv | 2 +- wally-pipelined/src/ebu/pagetablewalker.sv | 113 +++++++++--------- wally-pipelined/src/fpu/fpu.sv | 16 ++- wally-pipelined/src/ifu/icache.sv | 10 +- wally-pipelined/src/mmu/cam_line.sv | 5 +- wally-pipelined/src/mmu/tlb.sv | 6 +- wally-pipelined/src/mmu/tlb_ram.sv | 2 +- wally-pipelined/src/mmu/tlb_rand.sv | 2 +- wally-pipelined/src/muldiv/div.sv | 66 ++++------ wally-pipelined/src/privileged/csrc.sv | 2 +- .../src/wally/wallypipelinedhart.sv | 1 + 15 files changed, 113 insertions(+), 128 deletions(-) rename wally-pipelined/{src => misc}/tlb_toy/tlb_testbench.sv (100%) rename wally-pipelined/{src => misc}/tlb_toy/tlb_toy.sv.OLD (100%) rename wally-pipelined/{src => misc}/tlb_toy/tlb_toy.tv (100%) diff --git a/wally-pipelined/src/tlb_toy/tlb_testbench.sv b/wally-pipelined/misc/tlb_toy/tlb_testbench.sv similarity index 100% rename from wally-pipelined/src/tlb_toy/tlb_testbench.sv rename to wally-pipelined/misc/tlb_toy/tlb_testbench.sv diff --git a/wally-pipelined/src/tlb_toy/tlb_toy.sv.OLD b/wally-pipelined/misc/tlb_toy/tlb_toy.sv.OLD similarity index 100% rename from wally-pipelined/src/tlb_toy/tlb_toy.sv.OLD rename to wally-pipelined/misc/tlb_toy/tlb_toy.sv.OLD diff --git a/wally-pipelined/src/tlb_toy/tlb_toy.tv b/wally-pipelined/misc/tlb_toy/tlb_toy.tv similarity index 100% rename from wally-pipelined/src/tlb_toy/tlb_toy.tv rename to wally-pipelined/misc/tlb_toy/tlb_toy.tv diff --git a/wally-pipelined/src/cache/dmapped.sv b/wally-pipelined/src/cache/dmapped.sv index 9a51737a..f9d2bc8e 100644 --- a/wally-pipelined/src/cache/dmapped.sv +++ b/wally-pipelined/src/cache/dmapped.sv @@ -59,13 +59,13 @@ module rodirectmappedmem #(parameter LINESIZE = 256, parameter NUMLINES = 512, p // Swizzle bits to get the offset, set, and tag out of the read and write addresses always_comb begin // Read address - assign WordSelect = ReadLowerAdr[OFFSETWIDTH-1:0]; - assign ReadPAdr = {ReadUpperPAdr, ReadLowerAdr}; - assign ReadSet = ReadPAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; - assign ReadTag = ReadPAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; + WordSelect = ReadLowerAdr[OFFSETWIDTH-1:0]; + ReadPAdr = {ReadUpperPAdr, ReadLowerAdr}; + ReadSet = ReadPAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; + ReadTag = ReadPAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; // Write address - assign WriteSet = WritePAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; - assign WriteTag = WritePAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; + WriteSet = WritePAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; + WriteTag = WritePAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; end genvar i; @@ -85,8 +85,8 @@ module rodirectmappedmem #(parameter LINESIZE = 256, parameter NUMLINES = 512, p // Get the data and valid out of the lines always_comb begin - assign DataWord = LineOutputs[ReadSet]; - assign DataValid = ValidOutputs[ReadSet] & (TagOutputs[ReadSet] == ReadTag); + DataWord = LineOutputs[ReadSet]; + DataValid = ValidOutputs[ReadSet] & (TagOutputs[ReadSet] == ReadTag); end endmodule diff --git a/wally-pipelined/src/cache/line.sv b/wally-pipelined/src/cache/line.sv index e498d073..8b6e5e46 100644 --- a/wally-pipelined/src/cache/line.sv +++ b/wally-pipelined/src/cache/line.sv @@ -62,7 +62,7 @@ module rocacheline #(parameter LINESIZE = 256, parameter TAGSIZE = 32, parameter always_comb begin - assign DataWord = DataLinesOut[WordSelect[OFFSETSIZE-1:$clog2(WORDSIZE)]]; + DataWord = DataLinesOut[WordSelect[OFFSETSIZE-1:$clog2(WORDSIZE)]]; end endmodule diff --git a/wally-pipelined/src/ebu/pagetablewalker.sv b/wally-pipelined/src/ebu/pagetablewalker.sv index 83c1de84..357287aa 100644 --- a/wally-pipelined/src/ebu/pagetablewalker.sv +++ b/wally-pipelined/src/ebu/pagetablewalker.sv @@ -85,7 +85,7 @@ module pagetablewalker ( // Signals for direct, fake translations. Not part of the final Wally version. logic [`XLEN-1:0] DirectInstrPTE, DirectMemPTE; - logic [9:0] DirectPTEFlags = {2'b0, 8'b00001111}; + localparam DirectPTEFlags = {2'b0, 8'b00001111}; logic [`VPN_BITS-1:0] PCPageNumber, MemAdrPageNumber; @@ -133,17 +133,23 @@ module pagetablewalker ( assign PageTypeF = PageType; assign PageTypeM = PageType; + localparam IDLE = 3'h0; + localparam LEVEL1 = 3'h1; + localparam LEVEL0 = 3'h2; + localparam LEAF = 3'h3; + localparam FAULT = 3'h4; + localparam LEVEL2 = 3'h5; + + logic [2:0] WalkerState, NextWalkerState; + generate if (`XLEN == 32) begin logic [9:0] VPN1, VPN0; assign SvMode = SATP_REGW[31]; - typedef enum {IDLE, LEVEL1, LEVEL0, LEAF, FAULT} walker_statetype; - walker_statetype WalkerState, NextWalkerState; - // *** Do we need a synchronizer here for walker to talk to ahblite? - flopenl #(.TYPE(walker_statetype)) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(3) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); // State transition logic always_comb begin @@ -179,38 +185,38 @@ module pagetablewalker ( // Assign combinational outputs always_comb begin // default values - assign TranslationPAdr = '0; - assign PageTableEntry = '0; - assign PageType ='0; - assign MMUTranslationComplete = '0; - assign DTLBWriteM = '0; - assign ITLBWriteF = '0; - assign InstrPageFaultM = '0; - assign LoadPageFaultM = '0; - assign StorePageFaultM = '0; + TranslationPAdr = '0; + PageTableEntry = '0; + PageType ='0; + MMUTranslationComplete = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + InstrPageFaultM = '0; + LoadPageFaultM = '0; + StorePageFaultM = '0; case (NextWalkerState) LEVEL1: begin - assign TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; end LEVEL0: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; end LEAF: begin // Keep physical address alive to prevent HADDR dropping to 0 - assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - assign PageTableEntry = CurrentPTE; - assign PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - assign MMUTranslationComplete = '1; - assign DTLBWriteM = DTLBMissM; - assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; + MMUTranslationComplete = '1; + DTLBWriteM = DTLBMissM; + ITLBWriteF = ~DTLBMissM; // Prefer data over instructions end FAULT: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - assign MMUTranslationComplete = '1; - assign InstrPageFaultM = ~DTLBMissM; - assign LoadPageFaultM = DTLBMissM && ~MemStore; - assign StorePageFaultM = DTLBMissM && MemStore; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + MMUTranslationComplete = '1; + InstrPageFaultM = ~DTLBMissM; + LoadPageFaultM = DTLBMissM && ~MemStore; + StorePageFaultM = DTLBMissM && MemStore; end endcase end @@ -232,11 +238,8 @@ module pagetablewalker ( logic GigapageMisaligned, BadGigapage; - typedef enum {IDLE, LEVEL2, LEVEL1, LEVEL0, LEAF, FAULT} walker_statetype; - walker_statetype WalkerState, NextWalkerState; - // *** Do we need a synchronizer here for walker to talk to ahblite? - flopenl #(.TYPE(walker_statetype)) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(3) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb begin case (WalkerState) @@ -279,42 +282,42 @@ module pagetablewalker ( // *** Should translate this flop block into our flop module notation always_comb begin // default values - assign TranslationPAdr = '0; - assign PageTableEntry = '0; - assign PageType = '0; - assign MMUTranslationComplete = '0; - assign DTLBWriteM = '0; - assign ITLBWriteF = '0; - assign InstrPageFaultM = '0; - assign LoadPageFaultM = '0; - assign StorePageFaultM = '0; + TranslationPAdr = '0; + PageTableEntry = '0; + PageType = '0; + MMUTranslationComplete = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + InstrPageFaultM = '0; + LoadPageFaultM = '0; + StorePageFaultM = '0; case (NextWalkerState) LEVEL2: begin - assign TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; + TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; end LEVEL1: begin - assign TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; end LEVEL0: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; end LEAF: begin // Keep physical address alive to prevent HADDR dropping to 0 - assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - assign PageTableEntry = CurrentPTE; - assign PageType = (WalkerState == LEVEL2) ? 2'b11 : + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL2) ? 2'b11 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00); - assign MMUTranslationComplete = '1; - assign DTLBWriteM = DTLBMissM; - assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions + MMUTranslationComplete = '1; + DTLBWriteM = DTLBMissM; + ITLBWriteF = ~DTLBMissM; // Prefer data over instructions end FAULT: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - assign MMUTranslationComplete = '1; - assign InstrPageFaultM = ~DTLBMissM; - assign LoadPageFaultM = DTLBMissM && ~MemStore; - assign StorePageFaultM = DTLBMissM && MemStore; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + MMUTranslationComplete = '1; + InstrPageFaultM = ~DTLBMissM; + LoadPageFaultM = DTLBMissM && ~MemStore; + StorePageFaultM = DTLBMissM && MemStore; end endcase end @@ -331,4 +334,4 @@ module pagetablewalker ( end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index 9d58fd0f..91073c0e 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -22,6 +22,7 @@ module fpu ( //signals, modules, and combinational logic closely defined. //used for OSU DP-size hardware to wally XLEN interfacing + integer XLENDIFF; assign XLENDIFF = `XLEN - 64; integer XLENDIFFN; @@ -465,13 +466,18 @@ module fpu ( always_comb begin //zero extension - if(`XLEN > 64) begin - FPUResultW <= {FPUResultDirW,{XLENDIFF{1'b0}}}; - end + +// Teo 04/13/2021 +// Commented out XLENDIFF{1'b0} due to error: +// Repetition multiplier must be constant. + + //if(`XLEN > 64) begin + // FPUResultW <= {FPUResultDirW,{XLENDIFF{1'b0}}}; + //end //truncate - else begin + //else begin FPUResultW <= FPUResultDirW[63:64-`XLEN]; - end + //end end diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index 4208c355..10f52b59 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -94,9 +94,9 @@ module icache( // Read from memory if we don't have the address we want always_comb if (LastReadDataValidF & (InstrPAdrF == LastReadAdrF)) begin - assign InstrReadF = 0; + InstrReadF = 0; end else begin - assign InstrReadF = 1; + InstrReadF = 1; end // Pick from the memory input or from the previous read, as appropriate @@ -128,11 +128,11 @@ module icache( // incomplete, since the pipeline stalls for us when it isn't), or a NOP for // the cycle when the first of two reads comes in. always_comb if (~FlushDLastCyclen) begin - assign InstrDMuxChoice = 2'b10; + InstrDMuxChoice = 2'b10; end else if (DelayD & (MisalignedHalfInstrD[1:0] != 2'b11)) begin - assign InstrDMuxChoice = 2'b11; + InstrDMuxChoice = 2'b11; end else begin - assign InstrDMuxChoice = {1'b0, DelayD}; + InstrDMuxChoice = {1'b0, DelayD}; end mux4 #(32) instrDMux (AlignedInstrD, {InstrInF[15:0], MisalignedHalfInstrD}, nop, {16'b0, MisalignedHalfInstrD}, InstrDMuxChoice, InstrRawD); endmodule diff --git a/wally-pipelined/src/mmu/cam_line.sv b/wally-pipelined/src/mmu/cam_line.sv index 36765b27..e74ac53b 100644 --- a/wally-pipelined/src/mmu/cam_line.sv +++ b/wally-pipelined/src/mmu/cam_line.sv @@ -24,9 +24,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" -`include "wally-constants.vh" - module cam_line #(parameter KEY_BITS = 20, parameter HIGH_SEGMENT_BITS = 10) ( input clk, reset, @@ -76,4 +73,4 @@ module cam_line #(parameter KEY_BITS = 20, assign Match = ({1'b1, VirtualPageNumberQuery} == Key); -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 066e0c42..9aae039e 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -24,9 +24,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" -`include "wally-constants.vh" - /** * sv32 specs * ---------- @@ -52,6 +49,9 @@ * least recently) */ +`include "wally-config.vh" +`include "wally-constants.vh" + // The TLB will have 2**ENTRY_BITS total entries module tlb #(parameter ENTRY_BITS = 3) ( input clk, reset, diff --git a/wally-pipelined/src/mmu/tlb_ram.sv b/wally-pipelined/src/mmu/tlb_ram.sv index 059a9aa5..7e24a0a2 100644 --- a/wally-pipelined/src/mmu/tlb_ram.sv +++ b/wally-pipelined/src/mmu/tlb_ram.sv @@ -57,4 +57,4 @@ module tlb_ram #(parameter ENTRY_BITS = 3) ( ram[i] = `XLEN'b0; end -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/mmu/tlb_rand.sv b/wally-pipelined/src/mmu/tlb_rand.sv index 68a5acad..afb0bb2c 100644 --- a/wally-pipelined/src/mmu/tlb_rand.sv +++ b/wally-pipelined/src/mmu/tlb_rand.sv @@ -29,7 +29,7 @@ module tlb_rand #(parameter ENTRY_BITS = 3) ( ); logic [31:0] data; - assign data = $urandom; + assign data = 32'b0; assign WriteIndex = data[ENTRY_BITS-1:0]; endmodule diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index 38bdf0f0..78aea323 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -1479,21 +1479,15 @@ module shifter_l64 (Z, A, Shift); logic [63:0] stage3; logic [63:0] stage4; logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [63:0] Z; - mux2 #(64) mx01(A, {A[31:0], thirtytwozeros}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z); + mux2 #(64) mx01(A, {A[31:0], 32'h0}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {stage1[47:0], 16'h0}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {stage2[55:0], 8'h0}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {stage3[59:0], 4'h0}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {stage4[61:0], 2'h0}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {stage5[62:0], 1'h0}, Shift[0], Z); endmodule // shifter_l64 @@ -1507,21 +1501,15 @@ module shifter_r64 (Z, A, Shift); logic [63:0] stage3; logic [63:0] stage4; logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [63:0] Z; - mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {onezero, stage5[63:1]}, Shift[0], Z); + mux2 #(64) mx01(A, {32'h0, A[63:32]}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {16'h0, stage1[63:16]}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {8'h0, stage2[63:8]}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {4'h0, stage3[63:4]}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {2'h0, stage4[63:2]}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {1'h0, stage5[63:1]}, Shift[0], Z); endmodule // shifter_r64 @@ -1534,19 +1522,14 @@ module shifter_l32 (Z, A, Shift); logic [31:0] stage2; logic [31:0] stage3; logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [31:0] Z; - mux2 #(32) mx01(A, {A[15:0], sixteenzeros}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {stage3[29:0], twozeros}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {stage4[30:0], onezero}, Shift[0], Z); + mux2 #(32) mx01(A, {A[15:0], 16'h0}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {stage1[23:0], 8'h0}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {stage2[27:0], 4'h0}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {stage3[29:0], 2'h0}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {stage4[30:0], 1'h0}, Shift[0], Z); endmodule // shifter_l32 @@ -1559,19 +1542,14 @@ module shifter_r32 (Z, A, Shift); logic [31:0] stage2; logic [31:0] stage3; logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [31:0] Z; - mux2 #(32) mx01(A, {sixteenzeros, A[31:16]}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {onezero, stage4[31:1]}, Shift[0], Z); + mux2 #(32) mx01(A, {16'h0, A[31:16]}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {8'h0, stage1[31:8]}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {4'h0, stage2[31:4]}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {2'h0, stage3[31:2]}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {1'h0, stage4[31:1]}, Shift[0], Z); endmodule // shifter_r32 diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index dbf21e91..07ca9fb3 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -80,7 +80,7 @@ module csrc ( for (j=0; j<= `COUNTERS; j = j+1) begin // Write enables - if (j !==1) begin + if (j != 1) begin assign WriteHPMCOUNTERM[j] = CSRMWriteM && (CSRAdrM == MHPMCOUNTER[j]); // Count Signals assign HPMCOUNTERPlusM[j] = HPMCOUNTER_REGW[j] + {63'b0, MCOUNTEN[j] & ~MCOUNTINHIBIT_REGW[j]}; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 9b2bfe6a..18ef2a50 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -24,6 +24,7 @@ /////////////////////////////////////////// `include "wally-config.vh" +`include "wally-constants.vh" /* verilator lint_on UNUSED */ module wallypipelinedhart (