diff --git a/sim/wally-batch.do b/sim/wally-batch.do index 064f503b..3168b452 100644 --- a/sim/wally-batch.do +++ b/sim/wally-batch.do @@ -43,7 +43,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691 -fatal 7 + vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286 -fatal 7 run -all run -all @@ -52,7 +52,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=1 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7 + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 #-- Run the Simulation echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" @@ -63,7 +63,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { exec ./slack-notifier/slack-notifier.py } elseif {$2 eq "ahb"} { - vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 + vlog -lint -work wkdir/work_${1}_${2}_${3}_${4} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${2}_${3}_${4}.testbench -work wkdir/work_${1}_${2}_${3}_${4} -G TEST=$2 -o testbenchopt @@ -77,7 +77,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { run -all # power off -r /dut/core/* } else { - vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596 + vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt diff --git a/sim/wally.do b/sim/wally.do index 895b10b9..9b9fc30f 100644 --- a/sim/wally.do +++ b/sim/wally.do @@ -36,7 +36,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7 + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 #-- Run the Simulation #run -all @@ -50,7 +50,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7 + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 #-- Run the Simulation echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" @@ -68,7 +68,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } elseif {$2 eq "fpga"} { echo "hello" - vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063 + vlog -work work +incdir+../config/fpga +incdir+../config/shared ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286 vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt vsim workopt +nowarn3829 -fatal 7 @@ -78,10 +78,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } else { if {$2 eq "ahb"} { - vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4 } else { # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. - vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 + vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 } vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt diff --git a/sim/wave.do b/sim/wave.do index fcb6484d..6564e654 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -95,13 +95,15 @@ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCF +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F +add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 @@ -355,11 +357,6 @@ add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmach add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM @@ -631,7 +628,7 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Di add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {161886 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {394986 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -647,4 +644,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {161823 ns} {161929 ns} +WaveRestoreZoom {394883 ns} {395051 ns} diff --git a/testbench/testbench.sv b/testbench/testbench.sv index baf8980d..e811ea4b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -461,13 +461,36 @@ logic [3:0] dummy; .start(DCacheFlushStart), .done(DCacheFlushDone)); + // initialize the branch predictor - if (`BPRED_SUPPORTED == 1) - begin - genvar adrindex; - + if (`BPRED_SUPPORTED == 1) begin + integer adrindex; + + always @(*) begin + if(reset) begin + for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + end + for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin + force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + end + #1; + for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin + release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; + end + end + end + end + + + if (`BPRED_SUPPORTED == 1) begin +/* -----\/----- EXCLUDED -----\/----- + genvar adrindex; // Initializing all zeroes into the branch predictor memory. - for(adrindex = 0; adrindex < 2**10; adrindex++) begin + for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin initial begin force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; #1; @@ -481,6 +504,7 @@ logic [3:0] dummy; release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; end end + -----/\----- EXCLUDED -----/\----- */ if (`BPRED_LOGGER) begin string direction;