diff --git a/sim/imperas.ic b/sim/imperas.ic
index 930b6d3e..302773d0 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -1,21 +1,24 @@
-#--showoverrides
 --override cpu/show_c_prefix=T
 --override cpu/unaligned=F
 --override cpu/mstatus_FS=1
 --override cpu/ignore_non_leaf_DAU=1
 
 # Enable the Imperas instruction coverage
--extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
--override  refRoot/cpu/cv/cover=basic
--override  refRoot/cpu/cv/extensions=RV32I
+#-extlib    refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
+#-override  refRoot/cpu/cv/cover=basic
+#-override  refRoot/cpu/cv/extensions=RV32I
 
 # Add Imperas simulator application instruction tracing
 --trace
 --tracechange
 --traceshowicount
 --tracemode
+--tracemem ASX
 --monitornetschange
 
+# Exceptions and pagetables debug
+--override cpu/debugflags=6
+
 # Turn on verbose output for Imperas simulator
 --verbose
 
@@ -25,3 +28,9 @@
 # Store simulator output to logfile
 --output imperas.log
 
+--override cpu/PMP_registers=0
+#--showoverrides
+#--mpdconsole
+
+# ignore settings of bits DAU for non leaf page table walks
+--override cpu/ignore_non_leaf_DAU=1
diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do
index d08361e8..4164b7bd 100644
--- a/sim/wally-imperas.do
+++ b/sim/wally-imperas.do
@@ -46,10 +46,12 @@ vsim workopt +nowarn3829  -fatal 7 \
      +testDir=$env(TESTDIR) $env(OTHERFLAGS)
 view wave
 #-- display input and output signals as hexidecimal values
-add log -recursive /*
-do wave.do
+# add log -recursive /*
+# do wave.do
 
 run -all
 
 noview ../testbench/testbench_imperas.sv
 view wave
+
+quit -f
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index ce4b16de..e52a79c2 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -142,9 +142,10 @@ module testbench;
       if (!rvviVersionCheck(RVVI_API_VERSION)) begin
         msgfatal($sformatf("%m @ t=%0t: Expecting RVVI API version %0d.", $time, RVVI_API_VERSION));
       end
-      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,  "riscv.ovpworld.org"));
-      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,    "riscv"));
-      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GC"));
+      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR,         "riscv.ovpworld.org"));
+      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME,           "riscv"));
+      void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT,        "RV64GC"));
+      void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 39));
       if (!rvviRefInit(elffilename)) begin
         msgfatal($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
       end
@@ -163,11 +164,6 @@ module testbench;
           void'(rvviRefCsrSetVolatile(0, 32'hB82));   // MINSTRETH
       end
 
-  //    // Temporary fix for inexact difference
-//      void'(rvviRefCsrSetVolatile(0, 32'h001));   // fflags
-//      void'(rvviRefCsrSetVolatile(0, 32'h003));   // fcsr
-      
-      
       // Enable the trace2log module
       if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin
         msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE));