diff --git a/examples/asm/ch5/Makefile b/examples/asm/ch5/Makefile new file mode 100644 index 00000000..6f1cd89d --- /dev/null +++ b/examples/asm/ch5/Makefile @@ -0,0 +1,10 @@ +ch5.debug: ch5 + riscv64-unknown-elf-objdump -D ch5 > ch5.debug + +ch5: ch5.S Makefile + riscv64-unknown-elf-gcc -nodefaultlibs -nostartfiles -o ch5 ch5.S +# -ffreestanding +# -nostdlib + +clean: + rm -f ch5 ch5.debug \ No newline at end of file diff --git a/examples/asm/ch5/ch5 b/examples/asm/ch5/ch5 new file mode 100755 index 00000000..3684ea38 Binary files /dev/null and b/examples/asm/ch5/ch5 differ diff --git a/examples/asm/ch5/ch5.S b/examples/asm/ch5/ch5.S new file mode 100644 index 00000000..cfba5645 --- /dev/null +++ b/examples/asm/ch5/ch5.S @@ -0,0 +1,16 @@ +# ch5.s +# David_Harris@hmc.edu 14 December 2021 + +.section .text.init + +.globl _start +_start: + lw x1, 4(x0) + sw x1, 8(x0) + add x2, x1, x1 + beq x1, x2, done +loop: + jal x0, loop +done: + +.end diff --git a/examples/asm/ch5/ch5.debug b/examples/asm/ch5/ch5.debug new file mode 100644 index 00000000..28027a62 --- /dev/null +++ b/examples/asm/ch5/ch5.debug @@ -0,0 +1,38 @@ + +ch5: file format elf64-littleriscv + + +Disassembly of section .text: + +0000000000010078 <_start>: + 10078: 00402083 lw ra,4(zero) # 4 <_start-0x10074> + 1007c: 00102423 sw ra,8(zero) # 8 <_start-0x10070> + 10080: 00108133 add sp,ra,ra + 10084: 00208463 beq ra,sp,1008c + +0000000000010088 : + 10088: 0000006f j 10088 + +Disassembly of section .riscv.attributes: + +0000000000000000 <.riscv.attributes>: + 0: 3241 addiw tp,tp,-16 + 2: 0000 unimp + 4: 7200 ld s0,32(a2) + 6: 7369 lui t1,0xffffa + 8: 01007663 bgeu zero,a6,14 <_start-0x10064> + c: 0028 addi a0,sp,8 + e: 0000 unimp + 10: 7205 lui tp,0xfffe1 + 12: 3676 fld fa2,376(sp) + 14: 6934 ld a3,80(a0) + 16: 7032 0x7032 + 18: 5f30 lw a2,120(a4) + 1a: 326d addiw tp,tp,-5 + 1c: 3070 fld fa2,224(s0) + 1e: 615f 7032 5f30 0x5f307032615f + 24: 3266 fld ft4,120(sp) + 26: 3070 fld fa2,224(s0) + 28: 645f 7032 5f30 0x5f307032645f + 2e: 30703263 0x30703263 + ... diff --git a/examples/asm/ch5/example b/examples/asm/ch5/example new file mode 100755 index 00000000..a9b74047 Binary files /dev/null and b/examples/asm/ch5/example differ diff --git a/examples/asm/example/Makefile b/examples/asm/example/Makefile new file mode 100644 index 00000000..081f342c --- /dev/null +++ b/examples/asm/example/Makefile @@ -0,0 +1,2 @@ +example: example.S + riscv64-unknown-elf-gcc -o example example.S diff --git a/examples/asm/example/example b/examples/asm/example/example new file mode 100755 index 00000000..a9b74047 Binary files /dev/null and b/examples/asm/example/example differ diff --git a/examples/asm/example/example.S b/examples/asm/example/example.S new file mode 100644 index 00000000..f487950a --- /dev/null +++ b/examples/asm/example/example.S @@ -0,0 +1,67 @@ +// example.s +// David_Harris@hmc.edu 5 December 2021 + +.section .text.init +//.globl rvtest_entry_point +//rvtest_entry_point: + +.globl main +main: + li a0, 42 + +self_loop: + j self_loop + +.end + +/* +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32I") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + +RVTEST_SIGBASE( x3,signature_x3_1) + +inst_0: +// rs2 == rd != rs1, rs1==x4, rs2==x24, rd==x24, rs1_val > 0 and rs2_val > 0, rs2_val == 1, rs1_val == (2**(xlen-1)-1), rs1_val != rs2_val, rs1_val == 2147483647 +// opcode: add ; op1:x4; op2:x24; dest:x24; op1val:0x7fffffff; op2val:0x1 +TEST_RR_OP(add, x24, x4, x24, 0x80000000, 0x7fffffff, 0x1, x3, 0, x18) + + +80000000 : + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN +80000000: feedc0b7 lui ra,0xfeedc +8 + +80003220 : +#endif + + +RVTEST_CODE_END +RVMODEL_HALT +80003220: 00408093 addi ra,ra,4 +80003224: 00100093 li ra,1 + +80003228 : +80003228: 00001f17 auipc t5,0x1 +8000322c: dc1f2c23 sw ra,-552(t5) # 80004000 + +80003230 : +80003230: 0000006f j 80003230 +80003234: 0000 unimp + ... +*/ \ No newline at end of file diff --git a/examples/asm/test b/examples/asm/test new file mode 100755 index 00000000..fef7868c Binary files /dev/null and b/examples/asm/test differ diff --git a/examples/asm/test.S b/examples/asm/test.S new file mode 100644 index 00000000..0399a456 --- /dev/null +++ b/examples/asm/test.S @@ -0,0 +1,22 @@ +.globl main +.equ N, 5 + +.data +//A: .word 5, 42, −88, 2, −5033, 720, 314 +str1: .string "RISC-V" +.align 2 +B: .word 0x32A +.bss +C: .space +D: .space +.balign 4 + +.text +main: + li a0, 42 + jr ra + +.section .rodata +str2: .string "Hello" + +.end diff --git a/wally-pipelined/regression/fpga-wave.do b/wally-pipelined/regression/fpga-wave.do index a5916df3..43585e87 100644 --- a/wally-pipelined/regression/fpga-wave.do +++ b/wally-pipelined/regression/fpga-wave.do @@ -126,23 +126,17 @@ add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/r add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rd2 add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/we3 add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/wd3 -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ALUResultW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/IntResultW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ReadDataW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/A +add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/B +add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/ALUControl add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/flags +add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/FlagsEEEEE add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1E @@ -167,8 +161,8 @@ add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCE add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCM add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/InstrD -add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/SrcAE -add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/SrcBE +add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/ForwardedSrcAE +add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/ForwardedSrcBE add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/Funct3E add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/MulDivE add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/W64E diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do index 4532b932..ff0b82be 100644 --- a/wally-pipelined/regression/linux-wave.do +++ b/wally-pipelined/regression/linux-wave.do @@ -151,11 +151,11 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE add wave -noupdate -group alu -divider internals add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do index e7bf6067..097f3478 100644 --- a/wally-pipelined/regression/wave-all.do +++ b/wally-pipelined/regression/wave-all.do @@ -499,7 +499,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/TargetBaseE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultM -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultW +add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/IntResultW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/clk add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/reset @@ -562,27 +562,11 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/d0 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/d1 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/s add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/y -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/condinvb -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/presum -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sum -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/shift -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/slt -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sltu -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/bor -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/right -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/arith -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/w64 -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/ltu -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/A +add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/B +add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/ALUControl +add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/Result +add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/FlagsE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/a add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/amt add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/right diff --git a/wally-pipelined/regression/wave-coremark.do b/wally-pipelined/regression/wave-coremark.do index 5ce1a232..4d774046 100644 --- a/wally-pipelined/regression/wave-coremark.do +++ b/wally-pipelined/regression/wave-coremark.do @@ -130,11 +130,11 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE add wave -noupdate -group alu -divider internals add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 8bff207f..e8c76de0 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -127,23 +127,17 @@ add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW +add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/IntResultW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -168,8 +162,8 @@ add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM add wave -noupdate -expand -group PCS /testbench/PCW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD -add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE -add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE +add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE +add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E @@ -178,8 +172,6 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW -add wave -noupdate -group muldiv /testbench/dut/hart/mdu/genblk1/div/start -add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivDoneM add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N