From 967d89208885ec4d6a55e0d27825de3a5122b128 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 24 Dec 2022 10:21:16 -0600 Subject: [PATCH 1/2] Updated fpga constraints. --- fpga/constraints/debug2.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 480575aa..eed20184 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -356,7 +356,7 @@ connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/core/hzu/St create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe69] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69] -connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallD_inferred_i_2_n_0 ]] +connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/core/hzu/StallDCause08_in]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe70] From 0d6ce1d459c7d1018d8eb254cc1f408528e4338f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 24 Dec 2022 14:24:17 -0600 Subject: [PATCH 2/2] Fixed bug with the performance counters not updating. --- pipelined/src/privileged/csrc.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 5efa3ec0..e57fdfc7 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -67,7 +67,6 @@ module csrc #(parameter logic [4:0] CounterNumM; (* mark_debug = "true" *) logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0]; logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0]; - logic InstrValidNotFlushedM; logic LoadStallE, LoadStallM; logic [`COUNTERS-1:0] WriteHPMCOUNTERM; logic [`COUNTERS-1:0] CounterEvent;