diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 1b2ed42e..dbb852e8 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -233,7 +233,7 @@ module csr #(parameter .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, - .SATP_REGW, .MIP_REGW, .MIE_REGW, + .SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index bebad50d..aa4de62a 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -62,7 +62,7 @@ module csri #(parameter // SSIP is writable in SIP if S mode exists if (`S_SUPPORTED) begin:mask assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) - assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) + assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) assign MIE_WRITE_MASK = 12'hAAA; end else begin:mask assign MIP_WRITE_MASK = 12'h000; diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index 33ffa0ec..3a8e73ee 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -151,8 +151,8 @@ module csrm #(parameter // CSRs flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); if (`S_SUPPORTED) begin:deleg // DELEG registers should exist - flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW); - flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW); + flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, MEDELEG_REGW); + flopenr #(12) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM[11:0] & MIDELEG_MASK, MIDELEG_REGW); end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0; flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index d4000cdb..cf1a4d2f 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -61,7 +61,7 @@ module csrs #(parameter (* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW, output logic [31:0] SCOUNTEREN_REGW, output logic [`XLEN-1:0] SATP_REGW, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM ); @@ -102,7 +102,7 @@ module csrs #(parameter case (CSRAdrM) SSTATUS: CSRSReadValM = SSTATUS_REGW; STVEC: CSRSReadValM = STVEC_REGW; - SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222}; // only read supervisor fields + SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields // *** and with MIDELEG instead of 222 SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 8292b988..2918494d 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -8,6 +8,7 @@ wally_workdir = $(work)/wally-riscv-arch-test current_dir = $(shell pwd) #XLEN ?= 64 +#all: root wally32 wally64 all: root arch32 wally32 wally32e arch64 wally64 root: diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 82279e92..7dfe1f0a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -1295,6 +1295,12 @@ write_pmpaddr_end: addi a6, a6, 4 j test_loop +write_mideleg: + // writes the value in t4 to the mideleg register + // Doesn't log anything + csrw mideleg, t4 + j test_loop + executable_test: // Execute the code at the address in t3, returning the value in t2. // Assumes the code modifies t2, to become the value stored in t4 for this test. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S index b5a70625..414fb44b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S @@ -784,6 +784,7 @@ test_cases: # =========== S-mode enable tests (7.X) =========== +.4byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .4byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output .4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 .4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S index 68dcf82b..a6ed546a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S @@ -102,6 +102,7 @@ test_cases: # =========== Enter Supervisor Mode =========== +.4byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .4byte 0x0, 0x0, goto_s_mode # Enter supervisor mode # =========== Test interrupt enables and priorities =========== diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index bd43eb11..7310857a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -1335,6 +1335,12 @@ write_pmpaddr_end: addi a6, a6, 8 j test_loop +write_mideleg: + // writes the value in t4 to the mideleg register + // Doesn't log anything + csrw mideleg, t4 + j test_loop + executable_test: // Execute the code at the address in t3, returning the value in t2. // Assumes the code modifies t2, to become the value stored in t4 for this test. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S index 43ceabfc..b50b20f9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-01.S @@ -784,6 +784,7 @@ test_cases: # =========== S-mode enable tests (7.X) =========== +.8byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .8byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output .8byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 .8byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S index ed5063e8..5a6dc34e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-plic-s-01.S @@ -102,6 +102,7 @@ test_cases: # =========== Enter Supervisor Mode =========== +.8byte 0x0, 0x222, write_mideleg # delegate supervisor interrupts to S mode .8byte 0x0, 0x0, goto_s_mode # Enter supervisor mode # =========== Test interrupt enables and priorities ===========