From 0c307d2db13171ecf86e73019b552f885073d432 Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Tue, 20 Apr 2021 17:57:56 -0400 Subject: [PATCH] Fix synthesis warnings for privileged unit (replace 'initial' settings) --- wally-pipelined/src/privileged/csr.sv | 8 ++++++-- wally-pipelined/src/privileged/csrc.sv | 24 ++++++++++++++---------- wally-pipelined/src/privileged/csrm.sv | 23 ++++++++++++----------- wally-pipelined/src/privileged/csrs.sv | 24 +++++++++++++++--------- 4 files changed, 47 insertions(+), 32 deletions(-) diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index c6ee1996..b3572c7f 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -27,7 +27,11 @@ `include "wally-config.vh" -module csr ( +module csr #(parameter + // Constants + UIP_REGW = 12'b0, // N user-mode exceptions not supported + UIE_REGW = 12'b0 + ) ( input logic clk, reset, input logic FlushW, StallW, input logic [31:0] InstrM, @@ -64,7 +68,7 @@ module csr ( logic [11:0] CSRAdrM; logic [11:0] SIP_REGW, SIE_REGW; - logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported + //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported logic IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM; logic IllegalCSRMWriteReadonlyM; diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 07ca9fb3..b968af43 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -4,6 +4,8 @@ // Written: David_Harris@hmc.edu 9 January 2021 // Modified:ssanghai@hmc.edu 2nd March // Added a configurable number of counters +// dottolia@hmc.edu 20 April 2021 +// Make counters synthesizable // // Purpose: Counter CSRs // See RISC-V Privileged Mode Specification 20190608 3.1.10-11 @@ -45,18 +47,20 @@ module csrc ( integer HPMCOUNTERH [`COUNTERS:0]; integer MHPEVENT [`COUNTERS:0]; - initial begin - integer i; - for (i=0; i<= `COUNTERS; i = i+1) begin - if (i !==1) begin - MHPMCOUNTER[i] = 12'hB00 + i; // not sure this addition is legit - MHPMCOUNTERH[i] = 12'hB80 + i; - HPMCOUNTER[i] = 12'hC00 + i; - HPMCOUNTERH[i] = 12'hC80 + i; - MHPEVENT[i] = 12'h320 + i; // MHPEVENT[0] = MCOUNTERINHIBIT + genvar i; + generate + for (i = 0; i <= `COUNTERS; i = i + 1) begin + if (i != 1) begin + always @(posedge reset) begin + MHPMCOUNTER[i] = 12'hB00 + i; // not sure this addition is legit + MHPMCOUNTERH[i] = 12'hB80 + i; + HPMCOUNTER[i] = 12'hC00 + i; + HPMCOUNTERH[i] = 12'hC80 + i; + MHPEVENT[i] = 12'h320 + i; // MHPEVENT[0] = MCOUNTERINHIBIT + end end end //end for loop - end // end for initial + endgenerate logic [`COUNTERS:0] MCOUNTEN; assign MCOUNTEN[0] = 1'b1; diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 260e80d8..80fb509a 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -74,7 +74,12 @@ module csrm #(parameter DCSR = 12'h7B0, DPC = 12'h7B1, DSCRATCH0 = 12'h7B2, - DSCRATCH1 = 12'h7B3) ( + DSCRATCH1 = 12'h7B3, + ZERO = {(`XLEN){1'b0}}, + ALL_ONES = 32'hfffffff, + MEDELEG_MASK = ~(ZERO | 1'b1 << 11), + MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222} + ) ( input logic clk, reset, input logic CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, @@ -93,19 +98,15 @@ module csrm #(parameter logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // 64-bit registers in RV64, or two 32-bit registers in RV32 logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [0:15]; // *** Might have to make 16 individual registers //logic [`XLEN-1:0] PMPADDR0_REGW; - logic [`XLEN-1:0] zero = 0; - logic [31:0] allones = {32{1'b1}}; - logic [`XLEN-1:0] MEDELEG_MASK = ~(zero | 1'b1 << 11); // medeleg[11] hardwired to zero per Privileged Spec 3.1.8 - logic [`XLEN-1:0] MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}; // only allow delegating interrupts to supervisor mode + logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; logic WritePMPCFG0M, WritePMPCFG2M; logic WritePMPADDRM [0:15]; - logic [25:0] MISAbits = `MISA; // MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally - assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISAbits}; + assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, `MISA}; // Write machine Mode CSRs assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS); @@ -143,8 +144,8 @@ module csrm #(parameter flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0 generate if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist - flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, zero, MEDELEG_REGW); - flopenl #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, zero, MIDELEG_REGW); + flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, ZERO, MEDELEG_REGW); + flopenl #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, ZERO, MIDELEG_REGW); end else begin assign MEDELEG_REGW = 0; assign MIDELEG_REGW = 0; @@ -161,9 +162,9 @@ module csrm #(parameter if (`OVPSIM_CSR_CONFIG) flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW); else - flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW); + flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], ALL_ONES, MCOUNTEREN_REGW); endgenerate - flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], allones, MCOUNTINHIBIT_REGW); + flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], ALL_ONES, MCOUNTINHIBIT_REGW); // There are 16 PMPADDR registers, each of which has its own flop generate diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index 7f08d95a..c7c311da 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -39,7 +39,13 @@ module csrs #(parameter SCAUSE = 12'h142, STVAL = 12'h143, SIP= 12'h144, - SATP = 12'h180) ( + SATP = 12'h180, + + // Constants + ZERO = {(`XLEN){1'b0}}, + ALL_ONES = 32'hfffffff, + SEDELEG_MASK = ~(ZERO | 3'b111 << 9) + ) ( input logic clk, reset, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, @@ -54,9 +60,9 @@ module csrs #(parameter output logic IllegalCSRSAccessM ); - logic [`XLEN-1:0] zero = 0; - logic [31:0] allones = {32{1'b1}}; - logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 + //logic [`XLEN-1:0] zero = 0; + //logic [31:0] allones = {32{1'b1}}; + //logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 // Supervisor mode CSRs sometimes supported generate @@ -76,22 +82,22 @@ module csrs #(parameter assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN); // CSRs - flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, zero, STVEC_REGW); //busybear: change reset to 0 + flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, ZERO, STVEC_REGW); //busybear: change reset to 0 flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW); + flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, ZERO, SCAUSE_REGW); flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); if (`OVPSIM_CSR_CONFIG) flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW); else - flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW); + flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], ALL_ONES, SCOUNTEREN_REGW); if (`N_SUPPORTED) begin logic WriteSEDELEGM, WriteSIDELEGM; assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG); assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG); - flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW); - flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW); + flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, ZERO, SEDELEG_REGW); + flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, ZERO, SIDELEG_REGW); end else begin assign SEDELEG_REGW = 0; assign SIDELEG_REGW = 0;