From 0b3d3b768b873d77a4927ce6186d9a6a6ef3ee79 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 10 Jan 2022 16:26:18 +0000
Subject: [PATCH] Do file for riscvsingle

---
 examples/verilog/riscvsingle/riscvsingle.do   | 23 +++++++++++++++++++
 examples/verilog/riscvsingle/riscvsingle.sv   |  2 +-
 .../{riscvsingle.S => riscvtest.S}            |  0
 ...{riscvsingle.memfile => riscvtest.memfile} |  0
 4 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 examples/verilog/riscvsingle/riscvsingle.do
 rename examples/verilog/riscvsingle/{riscvsingle.S => riscvtest.S} (100%)
 rename examples/verilog/riscvsingle/{riscvsingle.memfile => riscvtest.memfile} (100%)

diff --git a/examples/verilog/riscvsingle/riscvsingle.do b/examples/verilog/riscvsingle/riscvsingle.do
new file mode 100644
index 00000000..41b1d88a
--- /dev/null
+++ b/examples/verilog/riscvsingle/riscvsingle.do
@@ -0,0 +1,23 @@
+# riscvsingle.do 
+# David_Harris@hmc.edu 10 January 2021
+
+# compile, optimize, and start the simulation
+vlog riscvsingle.sv 
+vopt +acc work.testbench -o workopt 
+vsim workopt
+
+# Add waveforms and run the simulation
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider "Main Datapath"
+add wave /testbench/dut/PC
+add wave /testbench/dut/Instr
+add wave /testbench/dut/rvsingle/dp/SrcA
+add wave /testbench/dut/rvsingle/dp/SrcB
+add wave /testbench/dut/rvsingle/dp/Result
+add wave -divider "Memory Bus"
+add wave /testbench/MemWrite
+add wave /testbench/DataAdr
+add wave /testbench/WriteData
+run -all
+view wave
diff --git a/examples/verilog/riscvsingle/riscvsingle.sv b/examples/verilog/riscvsingle/riscvsingle.sv
index 8fb662ae..2606e029 100644
--- a/examples/verilog/riscvsingle/riscvsingle.sv
+++ b/examples/verilog/riscvsingle/riscvsingle.sv
@@ -334,7 +334,7 @@ module imem(input  logic [31:0] a,
   logic [31:0] RAM[63:0];
 
   initial
-      $readmemh("riscvtest.txt",RAM);
+      $readmemh("riscvtest.memfile",RAM);
 
   assign rd = RAM[a[31:2]]; // word aligned
 endmodule
diff --git a/examples/verilog/riscvsingle/riscvsingle.S b/examples/verilog/riscvsingle/riscvtest.S
similarity index 100%
rename from examples/verilog/riscvsingle/riscvsingle.S
rename to examples/verilog/riscvsingle/riscvtest.S
diff --git a/examples/verilog/riscvsingle/riscvsingle.memfile b/examples/verilog/riscvsingle/riscvtest.memfile
similarity index 100%
rename from examples/verilog/riscvsingle/riscvsingle.memfile
rename to examples/verilog/riscvsingle/riscvtest.memfile