From 0af8151c2a746397faab772e6880023dcf3ebf07 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Sep 2022 03:57:57 -0700 Subject: [PATCH] Partitioned fdivsqrt into one module per file and added file names to opening comments --- pipelined/src/fpu/cvtshiftcalc.sv | 1 + pipelined/src/fpu/divshiftcalc.sv | 30 ++ pipelined/src/fpu/fclassify.sv | 1 + pipelined/src/fpu/fcmp.sv | 1 + pipelined/src/fpu/fctrl.sv | 1 + pipelined/src/fpu/fcvt.sv | 1 + pipelined/src/fpu/fdivsqrtfgen2.sv | 58 ++++ pipelined/src/fpu/fdivsqrtfgen4.sv | 55 ++++ pipelined/src/fpu/fdivsqrtqsel2.sv | 63 ++++ pipelined/src/fpu/fdivsqrtqsel4.sv | 112 +++++++ pipelined/src/fpu/fdivsqrtstage2.sv | 6 +- pipelined/src/fpu/fdivsqrtstage4.sv | 6 +- pipelined/src/fpu/fdivsqrtuotfc2.sv | 61 ++++ .../src/fpu/{otfc.sv => fdivsqrtuotfc4.sv} | 39 +-- pipelined/src/fpu/fhazard.sv | 2 +- pipelined/src/fpu/flags.sv | 1 + pipelined/src/fpu/fma.sv | 1 + pipelined/src/fpu/fmaadd.sv | 1 + pipelined/src/fpu/fmaalign.sv | 1 + pipelined/src/fpu/fmaexpadd.sv | 1 + pipelined/src/fpu/fmalza.sv | 1 + pipelined/src/fpu/fmamult.sv | 1 + pipelined/src/fpu/fmashiftcalc.sv | 1 + pipelined/src/fpu/fmasign.sv | 1 + pipelined/src/fpu/fpu.sv | 1 + pipelined/src/fpu/fregfile.sv | 1 + pipelined/src/fpu/fsgninj.sv | 1 + pipelined/src/fpu/negateintres.sv | 1 + pipelined/src/fpu/normshift.sv | 1 + pipelined/src/fpu/postprocess.sv | 1 + pipelined/src/fpu/qsel.sv | 277 ------------------ pipelined/src/fpu/resultsign.sv | 1 + pipelined/src/fpu/round.sv | 1 + pipelined/src/fpu/roundsign.sv | 1 + pipelined/src/fpu/shiftcorrection.sv | 1 + pipelined/src/fpu/specialcase.sv | 1 + pipelined/src/fpu/unpack.sv | 1 + pipelined/src/fpu/unpackinput.sv | 1 + 38 files changed, 416 insertions(+), 320 deletions(-) create mode 100644 pipelined/src/fpu/fdivsqrtfgen2.sv create mode 100644 pipelined/src/fpu/fdivsqrtfgen4.sv create mode 100644 pipelined/src/fpu/fdivsqrtqsel2.sv create mode 100644 pipelined/src/fpu/fdivsqrtqsel4.sv create mode 100644 pipelined/src/fpu/fdivsqrtuotfc2.sv rename pipelined/src/fpu/{otfc.sv => fdivsqrtuotfc4.sv} (74%) delete mode 100644 pipelined/src/fpu/qsel.sv diff --git a/pipelined/src/fpu/cvtshiftcalc.sv b/pipelined/src/fpu/cvtshiftcalc.sv index aef894f9..88382bdc 100644 --- a/pipelined/src/fpu/cvtshiftcalc.sv +++ b/pipelined/src/fpu/cvtshiftcalc.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// cvtshiftcalc.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/divshiftcalc.sv b/pipelined/src/fpu/divshiftcalc.sv index 8c66f809..2b1128ea 100644 --- a/pipelined/src/fpu/divshiftcalc.sv +++ b/pipelined/src/fpu/divshiftcalc.sv @@ -1,3 +1,33 @@ +/////////////////////////////////////////// +// divshiftcalc.sv +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Conversion shift calculation +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +////////////////////////////////////////////////////////////////////////////////////////////////`include "wally-config.vh" + `include "wally-config.vh" module divshiftcalc( diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index 6aaec00a..70049fcf 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fclassivy.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 48ff536f..923a1891 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -1,5 +1,6 @@ /////////////////////////////////////////// +// fcmp.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 50961f27..8f10611a 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fctrl.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index d2967887..b7f2f672 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -1,5 +1,6 @@ /////////////////////////////////////////// +// fcvt.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrtfgen2.sv new file mode 100644 index 00000000..2b952340 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtfgen2.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// fdivsqrtfgen2.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Radix 2 F Addend Generator +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtfgen2 ( + input logic sp, sz, + input logic [`DIVb+1:0] C, + input logic [`DIVb:0] U, UM, + output logic [`DIVb+3:0] F +); + logic [`DIVb+3:0] FP, FN, FZ; + logic [`DIVb+3:0] SExt, SMExt, CExt; + + assign SExt = {3'b0, U}; + assign SMExt = {3'b0, UM}; + assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k + + // Generate for both positive and negative bits + assign FP = ~(SExt << 1) & CExt; + assign FN = (SMExt << 1) | (CExt & ~(CExt << 2)); + assign FZ = '0; + + // Choose which adder input will be used + + always_comb + if (sp) F = FP; + else if (sz) F = FZ; + else F = FN; + +endmodule diff --git a/pipelined/src/fpu/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrtfgen4.sv new file mode 100644 index 00000000..b8559052 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtfgen4.sv @@ -0,0 +1,55 @@ +/////////////////////////////////////////// +// fdivsqrtfgen4.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtfgen4 ( + input logic [3:0] s, + input logic [`DIVb+3:0] C, U, UM, + output logic [`DIVb+3:0] F +); + logic [`DIVb+3:0] F2, F1, F0, FN1, FN2; + + // Generate for both positive and negative bits + assign F2 = (~U << 2) & (C << 2); + assign F1 = ~(U << 1) & C; + assign F0 = '0; + assign FN1 = (UM << 1) | (C & ~(C << 3)); + assign FN2 = (UM << 2) | ((C << 2)&~(C << 4)); + + // Choose which adder input will be used + + always_comb + if (s[3]) F = F2; + else if (s[2]) F = F1; + else if (s[1]) F = FN1; + else if (s[0]) F = FN2; + else F = F0; +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrtqsel2.sv new file mode 100644 index 00000000..98431673 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtqsel2.sv @@ -0,0 +1,63 @@ +/////////////////////////////////////////// +// fdivsqrtqsel2.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Radix 2 Quotient Digit Selection +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtqsel2 ( + input logic [3:0] ps, pc, + output logic qp, qz, qn +); + + logic [3:0] p, g; + logic magnitude, sign, cout; + + // The quotient selection logic is presented for simplicity, not + // for efficiency. You can probably optimize your logic to + // select the proper divisor with less delay. + + // Qmient equations from EE371 lecture notes 13-20 + assign p = ps ^ pc; + assign g = ps & pc; + + //assign magnitude = ~(&p[2:0]); + assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0])); + //assign sign = p[3] ^ cout; + assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & + (ps[0]^pc[0])); + assign sign = (ps[3]^pc[3])^ + (ps[2] & pc[2] | ((ps[2]^pc[2]) & + (ps[1]&pc[1] | ((ps[1]^pc[1]) & + (ps[0]&pc[0]))))); + + // Produce quotient = +1, 0, or -1 + assign qp = magnitude & ~sign; + assign qz = ~magnitude; + assign qn = magnitude & sign; +endmodule diff --git a/pipelined/src/fpu/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrtqsel4.sv new file mode 100644 index 00000000..6723b2d2 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtqsel4.sv @@ -0,0 +1,112 @@ +/////////////////////////////////////////// +// fdivsqrtqsel4.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Radix 4 Quotient Digit Selection +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fdivsqrtqsel4 ( + input logic [`DIVN-2:0] D, + input logic [4:0] Smsbs, + input logic [`DIVb+3:0] WS, WC, + input logic Sqrt, j1, + output logic [3:0] q +); + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] Dmsbs, A; + + assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; + assign Wmsbs = PreWmsbs[7:1]; + assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; + // D = 0001.xxx... + // Dmsbs = | | + // W = xxxx.xxx... + // Wmsbs = | | + + logic [3:0] QSel4[1023:0]; + + always_comb begin + integer a, w, i, w2; + for(a=0; a<8; a++) + for(w=0; w<128; w++)begin + i = a*128+w; + w2 = w-128*(w>=64); // convert to two's complement + case(a) + 0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-4) QSel4[i] = 4'b0000; + else if(w2>=-13) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 1: if(w2>=14) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-4) QSel4[i] = 4'b0000; + else if(w2>=-14) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 2: if(w2>=16) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-6) QSel4[i] = 4'b0000; + else if(w2>=-16) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 3: if(w2>=16) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-6) QSel4[i] = 4'b0000; + else if(w2>=-17) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 4: if(w2>=18) QSel4[i] = 4'b1000; + else if(w2>=6) QSel4[i] = 4'b0100; + else if(w2>=-6) QSel4[i] = 4'b0000; + else if(w2>=-18) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 5: if(w2>=20) QSel4[i] = 4'b1000; + else if(w2>=6) QSel4[i] = 4'b0100; + else if(w2>=-8) QSel4[i] = 4'b0000; + else if(w2>=-20) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 6: if(w2>=20) QSel4[i] = 4'b1000; + else if(w2>=8) QSel4[i] = 4'b0100; + else if(w2>=-8) QSel4[i] = 4'b0000; + else if(w2>=-22) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 7: if(w2>=24) QSel4[i] = 4'b1000; + else if(w2>=8) QSel4[i] = 4'b0100; + else if(w2>=-8) QSel4[i] = 4'b0000; + else if(w2>=-22) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + endcase + end + end + always_comb + if (Sqrt) begin + if (j1) A = 3'b101; + else if (Smsbs == 5'b10000) A = 3'b111; + else A = Smsbs[2:0]; + end else A = Dmsbs; + assign q = QSel4[{A,Wmsbs}]; + +endmodule diff --git a/pipelined/src/fpu/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrtstage2.sv index 1671ddaa..7c48e9a9 100644 --- a/pipelined/src/fpu/fdivsqrtstage2.sv +++ b/pipelined/src/fpu/fdivsqrtstage2.sv @@ -60,8 +60,8 @@ module fdivsqrtstage2 ( // 0000 = 0 // 0010 = -1 // 0001 = -2 - qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn); - fgen2 fgen2(.sp(qp), .sz(qz), .C(CNext), .U, .UM, .F); + fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz, qn); + fdivsqrtfgen2 fgen2(.sp(qp), .sz(qz), .C(CNext), .U, .UM, .F); assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}); // Partial Product Generation @@ -69,7 +69,7 @@ module fdivsqrtstage2 ( assign AddIn = SqrtM ? F : Dsel; csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); - uotfc2 uotfc2(.sp(qp), .sz(qz), .C(CNext), .U, .UM, .UNext, .UMNext); + fdivsqrtuotfc2 uotfc2(.sp(qp), .sz(qz), .C(CNext), .U, .UM, .UNext, .UMNext); endmodule diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv index 9f70b9c2..a98c4ae6 100644 --- a/pipelined/src/fpu/fdivsqrtstage4.sv +++ b/pipelined/src/fpu/fdivsqrtstage4.sv @@ -62,8 +62,8 @@ module fdivsqrtstage4 ( // 0010 = -1 // 0001 = -2 assign Smsbs = U[`DIVb:`DIVb-4]; - qsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .q); - fgen4 fgen4(.s(q), .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F); + fdivsqrtqsel4 qsel4(.D, .Smsbs, .WS, .WC, .Sqrt(SqrtM), .j1, .q); + fdivsqrtfgen4 fgen4(.s(q), .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F); always_comb case (q) @@ -81,7 +81,7 @@ module fdivsqrtstage4 ( assign CarryIn = ~SqrtM & (q[3] | q[2]); // +1 for 2's complement of -D and -2D csa #(`DIVb+4) csa(WS, WC, AddIn, CarryIn, WSA, WCA); - uotfc4 uotfc4(.s(q), .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext); + fdivsqrtuotfc4 fdivsqrtuotfc4(.s(q), .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .U, .UM, .UNext, .UMNext); assign qn = 0; // unused for radix 4 endmodule diff --git a/pipelined/src/fpu/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrtuotfc2.sv new file mode 100644 index 00000000..b283ed05 --- /dev/null +++ b/pipelined/src/fpu/fdivsqrtuotfc2.sv @@ -0,0 +1,61 @@ +/////////////////////////////////////////// +// fdivsqrtuotfc2.sv +// +// Written: me@KatherineParry.com, cturek@hmc.edu +// Modified:7/14/2022 +// +// Purpose: Radix 2 unified on-the-fly converter +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +/////////////////////////////// +// Unified OTFC, Radix 2 // +/////////////////////////////// +module fdivsqrtuotfc2( + input logic sp, sz, + input logic [`DIVb+1:0] C, + input logic [`DIVb:0] U, UM, + output logic [`DIVb:0] UNext, UMNext +); + // The on-the-fly converter transfers the divsqrt + // bits to the quotient as they come. + logic [`DIVb:0] K; + + assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1)); + + always_comb begin + if (sp) begin + UNext = U | K; + UMNext = U; + end else if (sz) begin + UNext = U; + UMNext = UM | K; + end else begin // If sp and sz are not true, then sn is + UNext = UM | K; + UMNext = UM; + end + end + +endmodule diff --git a/pipelined/src/fpu/otfc.sv b/pipelined/src/fpu/fdivsqrtuotfc4.sv similarity index 74% rename from pipelined/src/fpu/otfc.sv rename to pipelined/src/fpu/fdivsqrtuotfc4.sv index cc4ab534..4c4f4040 100644 --- a/pipelined/src/fpu/otfc.sv +++ b/pipelined/src/fpu/fdivsqrtuotfc4.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// -// otfc.sv +// fdivsqrtuotfc4.sv // // Written: me@KatherineParry.com, cturek@hmc.edu // Modified:7/14/2022 // -// Purpose: On the fly conversion +// Purpose: Radix 4 unified on-the-fly converter // // A component of the Wally configurable RISC-V project. // @@ -30,40 +30,7 @@ `include "wally-config.vh" -/////////////////////////////// -// Un ified OTFC, Radix 2 // -/////////////////////////////// -module uotfc2( - input logic sp, sz, - input logic [`DIVb+1:0] C, - input logic [`DIVb:0] U, UM, - output logic [`DIVb:0] UNext, UMNext -); - // The on-the-fly converter transfers the divsqrt - // bits to the quotient as they come. - logic [`DIVb:0] K; - - assign K = (C[`DIVb:0] & ~(C[`DIVb:0] << 1)); - - always_comb begin - if (sp) begin - UNext = U | K; - UMNext = U; - end else if (sz) begin - UNext = U; - UMNext = UM | K; - end else begin // If sp and sz are not true, then sn is - UNext = UM | K; - UMNext = UM; - end - end - -endmodule - -/////////////////////////////// -// Unified OTFC, Radix 4 // -/////////////////////////////// -module uotfc4( +module fdivsqrtuotfc4( input logic [3:0] s, input logic Sqrt, input logic [`DIVb:0] U, UM, diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index 690e04eb..4b61f2bf 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// fpuhazard.sv +// fhazard.sv // // Written: me@KatherineParry.com 19 May 2021 // Modified: diff --git a/pipelined/src/fpu/flags.sv b/pipelined/src/fpu/flags.sv index 73cc3ae3..952e0c02 100644 --- a/pipelined/src/fpu/flags.sv +++ b/pipelined/src/fpu/flags.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// flags.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index d12f497e..fa71d905 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fma.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmaadd.sv b/pipelined/src/fpu/fmaadd.sv index af7b15bf..2b5d2c4a 100644 --- a/pipelined/src/fpu/fmaadd.sv +++ b/pipelined/src/fpu/fmaadd.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmaadd.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmaalign.sv b/pipelined/src/fpu/fmaalign.sv index f7c84999..6c657738 100644 --- a/pipelined/src/fpu/fmaalign.sv +++ b/pipelined/src/fpu/fmaalign.sv @@ -1,5 +1,6 @@ /////////////////////////////////////////// +// fmaalign.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmaexpadd.sv b/pipelined/src/fpu/fmaexpadd.sv index d39dfadd..33919d7a 100644 --- a/pipelined/src/fpu/fmaexpadd.sv +++ b/pipelined/src/fpu/fmaexpadd.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmaexpadd.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmalza.sv b/pipelined/src/fpu/fmalza.sv index 8e92a5dc..1f6677dd 100644 --- a/pipelined/src/fpu/fmalza.sv +++ b/pipelined/src/fpu/fmalza.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmalza.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmamult.sv b/pipelined/src/fpu/fmamult.sv index 1e1b0981..071b3e6c 100644 --- a/pipelined/src/fpu/fmamult.sv +++ b/pipelined/src/fpu/fmamult.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmamult.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fmashiftcalc.sv b/pipelined/src/fpu/fmashiftcalc.sv index a1c0a276..03209ca9 100644 --- a/pipelined/src/fpu/fmashiftcalc.sv +++ b/pipelined/src/fpu/fmashiftcalc.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmashiftcalc.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/fmasign.sv b/pipelined/src/fpu/fmasign.sv index 936eea21..aaeeb15c 100644 --- a/pipelined/src/fpu/fmasign.sv +++ b/pipelined/src/fpu/fmasign.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fmasign.sv // // Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu // Modified: diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 84109b61..b6eb25d2 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fpu.sv // // Written: me@KatherineParry.com, James Stine, Brett Mathis // Modified: 6/23/2021 diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index 00c89ff5..f738fc8a 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fregfile.sv // // Written: David_Harris@hmc.edu 9 January 2021 // Modified: James Stine diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index a5b7e774..a8556998 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// fsgninj.sv // // Written: me@KatherineParry.com // Modified: 6/23/2021 diff --git a/pipelined/src/fpu/negateintres.sv b/pipelined/src/fpu/negateintres.sv index 7a696b37..5e8959ff 100644 --- a/pipelined/src/fpu/negateintres.sv +++ b/pipelined/src/fpu/negateintres.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// negateintres.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/normshift.sv b/pipelined/src/fpu/normshift.sv index f2ceb1a3..0d23d2f7 100644 --- a/pipelined/src/fpu/normshift.sv +++ b/pipelined/src/fpu/normshift.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// normshift.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv index 145eac12..ee18c4bc 100644 --- a/pipelined/src/fpu/postprocess.sv +++ b/pipelined/src/fpu/postprocess.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// postprocess.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/qsel.sv b/pipelined/src/fpu/qsel.sv deleted file mode 100644 index 84614197..00000000 --- a/pipelined/src/fpu/qsel.sv +++ /dev/null @@ -1,277 +0,0 @@ -/////////////////////////////////////////// -// srt.sv -// -// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu -// Modified:13 January 2022 -// -// Purpose: Combined Divide and Square Root Floating Point and Integer Unit -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module qsel2 ( // *** eventually just change to 4 bits - input logic [3:0] ps, pc, - output logic qp, qz, qn -); - - logic [3:0] p, g; - logic magnitude, sign, cout; - - // The quotient selection logic is presented for simplicity, not - // for efficiency. You can probably optimize your logic to - // select the proper divisor with less delay. - - // Qmient equations from EE371 lecture notes 13-20 - assign p = ps ^ pc; - assign g = ps & pc; - - //assign magnitude = ~(&p[2:0]); - assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0])); - //assign sign = p[3] ^ cout; - assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & - (ps[0]^pc[0])); - assign sign = (ps[3]^pc[3])^ - (ps[2] & pc[2] | ((ps[2]^pc[2]) & - (ps[1]&pc[1] | ((ps[1]^pc[1]) & - (ps[0]&pc[0]))))); - - // Produce quotient = +1, 0, or -1 - assign qp = magnitude & ~sign; - assign qz = ~magnitude; - assign qn = magnitude & sign; -endmodule - -//////////////////////////////////// -// Adder Input Generation, Radix 2 // -//////////////////////////////////// -module fgen2 ( - input logic sp, sz, - input logic [`DIVb+1:0] C, - input logic [`DIVb:0] U, UM, - output logic [`DIVb+3:0] F -); - logic [`DIVb+3:0] FP, FN, FZ; - logic [`DIVb+3:0] SExt, SMExt, CExt; - - assign SExt = {3'b0, U}; - assign SMExt = {3'b0, UM}; - assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k - - // Generate for both positive and negative bits - assign FP = ~(SExt << 1) & CExt; - assign FN = (SMExt << 1) | (CExt & ~(CExt << 2)); - assign FZ = '0; - - // Choose which adder input will be used - - always_comb - if (sp) F = FP; - else if (sz) F = FZ; - else F = FN; - -endmodule - -module qsel4 ( - input logic [`DIVN-2:0] D, - input logic [4:0] Smsbs, - input logic [`DIVb+3:0] WS, WC, - input logic Sqrt, j1, - output logic [3:0] q -); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] Dmsbs, A; - - assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; - assign Wmsbs = PreWmsbs[7:1]; - assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; - // D = 0001.xxx... - // Dmsbs = | | - // W = xxxx.xxx... - // Wmsbs = | | - - logic [3:0] QSel4[1023:0]; - - always_comb begin - integer a, w, i, w2; - for(a=0; a<8; a++) - for(w=0; w<128; w++)begin - i = a*128+w; - w2 = w-128*(w>=64); // convert to two's complement - case(a) - 0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-4) QSel4[i] = 4'b0000; - else if(w2>=-13) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 1: if(w2>=14) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-4) QSel4[i] = 4'b0000; - else if(w2>=-14) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 2: if(w2>=16) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-16) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 3: if(w2>=16) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-17) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 4: if(w2>=18) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-18) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 5: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-20) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 6: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-22) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 7: if(w2>=24) QSel4[i] = 4'b1000; - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-22) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - endcase - end - end - always_comb - if (Sqrt) begin - if (j1) A = 3'b101; - else if (Smsbs == 5'b10000) A = 3'b111; - else A = Smsbs[2:0]; - end else A = Dmsbs; - assign q = QSel4[{A,Wmsbs}]; - -endmodule - -// qsel4old was working for divide -module qsel4old ( - input logic [`DIVN-2:0] D, - input logic [`DIVb+3:0] WS, WC, - input logic Sqrt, - output logic [3:0] q -); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] Dmsbs; - assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; - assign Wmsbs = PreWmsbs[7:1]; - assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; - // D = 0001.xxx... - // Dmsbs = | | - // W = xxxx.xxx... - // Wmsbs = | | - - logic [3:0] QSel4[1023:0]; - - always_comb begin - integer d, w, i, w2; - for(d=0; d<8; d++) - for(w=0; w<128; w++)begin - i = d*128+w; - w2 = w-128*(w>=64); // convert to two's complement - case(d) - 0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-4) QSel4[i] = 4'b0000; - else if(w2>=-13) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 1: if(w2>=14) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-5) QSel4[i] = 4'b0000; // was -6 - else if(~Sqrt&(w2>=-15)) QSel4[i] = 4'b0010; // divide case - else if( Sqrt&(w2>=-14)) QSel4[i] = 4'b0010; // sqrt case - else QSel4[i] = 4'b0001; - 2: if(w2>=15) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-16) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 3: if(w2>=16) QSel4[i] = 4'b1000; - else if(w2>=4) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; - else if(w2>=-17) QSel4[i] = 4'b0010; // was -18 - else QSel4[i] = 4'b0001; - 4: if(w2>=18) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-6) QSel4[i] = 4'b0000; // was -8 - else if(~Sqrt&(w2>=-20)) QSel4[i] = 4'b0010; // divide case - else if( Sqrt&(w2>=-18)) QSel4[i] = 4'b0010; // sqrt case - else QSel4[i] = 4'b0001; - 5: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=6) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-20) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 6: if(w2>=20) QSel4[i] = 4'b1000; - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-22) QSel4[i] = 4'b0010; - else QSel4[i] = 4'b0001; - 7: if(w2>=22) QSel4[i] = 4'b1000; // was 24 - else if(w2>=8) QSel4[i] = 4'b0100; - else if(w2>=-8) QSel4[i] = 4'b0000; - else if(w2>=-23) QSel4[i] = 4'b0010; // was -24 ***use -22 - else QSel4[i] = 4'b0001; - endcase - end - end - assign q = QSel4[{Dmsbs,Wmsbs}]; - -endmodule - -//////////////////////////////////// -// Adder Input Generation, Radix 4 // -//////////////////////////////////// -module fgen4 ( - input logic [3:0] s, - input logic [`DIVb+3:0] C, U, UM, - output logic [`DIVb+3:0] F -); - logic [`DIVb+3:0] F2, F1, F0, FN1, FN2; - - // Generate for both positive and negative bits - assign F2 = (~U << 2) & (C << 2); - assign F1 = ~(U << 1) & C; - assign F0 = '0; - assign FN1 = (UM << 1) | (C & ~(C << 3)); - assign FN2 = (UM << 2) | ((C << 2)&~(C << 4)); - - // Choose which adder input will be used - - always_comb - if (s[3]) F = F2; - else if (s[2]) F = F1; - else if (s[1]) F = FN1; - else if (s[0]) F = FN2; - else F = F0; -endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/resultsign.sv b/pipelined/src/fpu/resultsign.sv index 8d6dbb6e..cd7a096f 100644 --- a/pipelined/src/fpu/resultsign.sv +++ b/pipelined/src/fpu/resultsign.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// resultsign.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/round.sv b/pipelined/src/fpu/round.sv index d33d894a..e4450325 100644 --- a/pipelined/src/fpu/round.sv +++ b/pipelined/src/fpu/round.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// round.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/roundsign.sv b/pipelined/src/fpu/roundsign.sv index 62e882e6..1618f501 100644 --- a/pipelined/src/fpu/roundsign.sv +++ b/pipelined/src/fpu/roundsign.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// roundsign.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/shiftcorrection.sv b/pipelined/src/fpu/shiftcorrection.sv index 01be2f3f..eca97bcf 100644 --- a/pipelined/src/fpu/shiftcorrection.sv +++ b/pipelined/src/fpu/shiftcorrection.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// shiftcorrection.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/specialcase.sv b/pipelined/src/fpu/specialcase.sv index 41e75110..19d60ba7 100644 --- a/pipelined/src/fpu/specialcase.sv +++ b/pipelined/src/fpu/specialcase.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// specialcase.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv index 4053cba1..8444a2c6 100644 --- a/pipelined/src/fpu/unpack.sv +++ b/pipelined/src/fpu/unpack.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// unpack.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022 diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index 4e43768c..bf524698 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -1,4 +1,5 @@ /////////////////////////////////////////// +// unpackinput.sv // // Written: me@KatherineParry.com // Modified: 7/5/2022