From 56813ea496f56572f2ae46fbd63dcd05cecae420 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Wed, 27 Oct 2021 13:45:56 -0700 Subject: [PATCH 1/7] Added instructions to enable buildroot tests and updated some paths in README.md --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index 420ea87a..fd305294 100644 --- a/README.md +++ b/README.md @@ -8,6 +8,7 @@ To use Wally on Linux: ``` git clone https://github.com/davidharrishmc/riscv-wally cd riscv-wally +cd tests cd imperas-riscv-tests make cd ../addins @@ -30,6 +31,8 @@ edit Makefile.include make make XLEN=32 exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim +cd ../../wally-pipelined/linux-testgen/linux-testvectors +./tvLinker.sh ``` Notes: From c9ac0c0769fa7ea0be6707232b78ebf5871ded52 Mon Sep 17 00:00:00 2001 From: davidharrishmc <74973295+davidharrishmc@users.noreply.github.com> Date: Tue, 16 Nov 2021 12:33:47 -0800 Subject: [PATCH 2/7] Update README.md updated linux_testvectors path --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index b97a5efd..bbde2614 100644 --- a/README.md +++ b/README.md @@ -39,7 +39,7 @@ cd ../wally-riscv-arch-test make make XLEN=32 exe2memfile.pl work/*/*/*.elf # converts ELF files to a format that can be read by Modelsim -cd ../../tests/linux-testgen/linux-testvectors +cd ../linux-testgen/linux-testvectors ./tvLinker.sh ``` From 6fde97b16c23210b6c438aa99ea5e8b919ec9c0d Mon Sep 17 00:00:00 2001 From: Skylar Litz Date: Tue, 16 Nov 2021 16:46:17 -0800 Subject: [PATCH 3/7] fixed interrupt timing bug --- wally-pipelined/testbench/testbench-linux.sv | 48 +++++--------------- 1 file changed, 12 insertions(+), 36 deletions(-) diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index eb820c13..3db2f8cb 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -419,18 +419,6 @@ module testbench(); CheckMIPFutureE = 1; \ NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \ end \ - // $display("%tn: ExpectedCSRArrayM[7] (MEPC) = %x",$time,ExpectedCSRArrayM[7]); \ - // $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); \ - // // if PC does not equal MEPC, request delayed MIP is True \ - // if(ExpectedPCM != ExpectedCSRArrayM[7]) begin \ - // RequestDelayedMIP = 1; \ - // end else begin \ - // $display("%tns: Updating MIP to %x",$time,ExpectedCSRArrayValueM[NumCSRM]); \ - // MIPexpected = ExpectedCSRArrayValueM[NumCSRM]; \ - // force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; \ - // end \ - // end \ - // $display("%tns: ExpectedCSRArrayM::: %p",$time,ExpectedCSRArrayM); \ if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \ $display("hello! we are here."); \ MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \ @@ -468,11 +456,10 @@ module testbench(); if(CheckMIPFutureE) CheckMIPFutureE <= 0; CheckMIPFutureM <= CheckMIPFutureE; if(CheckMIPFutureM) begin - $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); - $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); - $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); + // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM); + // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE); + // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW); if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 16)) begin - // if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin RequestDelayedMIP <= 1; $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); end else begin // update MIP immediately @@ -480,29 +467,18 @@ module testbench(); MIPexpected = NextMIPexpected; force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; end - $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); - $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); - $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM); - $display("%tn: MepcExpected = %x",$time,MepcExpected); - $display("%tn: ExpectedPCM = %x",$time,ExpectedPCM); - // if PC does not equal MEPC, request delayed MIP is True - $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM)); - $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]); - $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]); - - // if((ExpectedPCM != MepcExpected) & ((MepcExpected - ExpectedPCM) * (MepcExpected - ExpectedPCM) <= 16)) begin - // RequestDelayedMIP = 1; - // $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected); - // end else begin - // $display("%tns: Updating MIP to %x",$time,NextMIPexpected); - // MIPexpected = NextMIPexpected; - // force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; - // end + // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM); + // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM); + // $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM); + // $display("%tn: MepcExpected = %x",$time,MepcExpected); + // $display("%tn: ExpectedPCE = %x",$time,ExpectedPCE); + // $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE)); + // $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]); + // $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]); end - if(RequestDelayedMIP) begin + if(RequestDelayedMIP & checkInstrM) begin $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); $display("%tns: Updating MIP to %x",$time,NextMIPexpected); - $display("%tns: MepcExpected %x",$time,MepcExpected); MIPexpected = NextMIPexpected; force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected; $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW); From 7a8c21e71f8ac3ba2b4f3a88c0710c06baadf0c9 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 17 Nov 2021 10:53:17 -0800 Subject: [PATCH 4/7] renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv --- wally-pipelined/regression/wave-all.do | 2 +- wally-pipelined/src/ieu/datapath.sv | 14 ++++++++------ wally-pipelined/src/ieu/ieu.sv | 1 + wally-pipelined/src/muldiv/intdivrestoring.sv | 13 +++++++------ wally-pipelined/src/muldiv/mul.sv | 15 ++++++++------- wally-pipelined/src/muldiv/muldiv.sv | 5 +++-- wally-pipelined/src/wally/wallypipelinedhart.sv | 2 +- 7 files changed, 29 insertions(+), 23 deletions(-) diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do index f587ec8f..98e04c47 100644 --- a/wally-pipelined/regression/wave-all.do +++ b/wally-pipelined/regression/wave-all.do @@ -492,7 +492,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD1E add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/RD2E add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ExtImmE -add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/PreSrcAE +add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ForwardedSrcAE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/SrcBE add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index 2ebd65d8..838d83a7 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -43,6 +43,7 @@ module datapath ( input logic [`XLEN-1:0] PCLinkE, output logic [2:0] FlagsE, output logic [`XLEN-1:0] PCTargetE, + output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B output logic [`XLEN-1:0] SrcAE, SrcBE, // Memory stage signals input logic StallM, FlushM, @@ -73,7 +74,8 @@ module datapath ( logic [`XLEN-1:0] RD1E, RD2E; logic [`XLEN-1:0] ExtImmE; - logic [`XLEN-1:0] PreSrcAE, PreSrcBE, SrcAE2, SrcBE2; + // logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path. + logic [`XLEN-1:0] SrcAE2, SrcBE2; logic [`XLEN-1:0] ALUResultE; logic [`XLEN-1:0] WriteDataE; @@ -104,12 +106,12 @@ module datapath ( flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); - mux3 #(`XLEN) faemux(RD1E, WriteDataW, ResultM, ForwardAE, PreSrcAE); - mux3 #(`XLEN) fbemux(RD2E, WriteDataW, ResultM, ForwardBE, PreSrcBE); - mux2 #(`XLEN) writedatamux(PreSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); - mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE); + mux3 #(`XLEN) faemux(RD1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE); + mux3 #(`XLEN) fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE); + mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); + mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2); - mux2 #(`XLEN) srcbmux(PreSrcBE, ExtImmE, ALUSrcBE, SrcBE); + mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE); mux2 #(`XLEN) srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux. alu #(`XLEN) alu(SrcAE2, SrcBE2, ALUControlE, ALUResultE, FlagsE); mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index d3babff3..e9c6d117 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -40,6 +40,7 @@ module ieu ( output logic [`XLEN-1:0] PCTargetE, output logic MulDivE, W64E, output logic [2:0] Funct3E, + output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B output logic [`XLEN-1:0] SrcAE, SrcBE, input logic FWriteIntM, diff --git a/wally-pipelined/src/muldiv/intdivrestoring.sv b/wally-pipelined/src/muldiv/intdivrestoring.sv index 806015f1..51604698 100644 --- a/wally-pipelined/src/muldiv/intdivrestoring.sv +++ b/wally-pipelined/src/muldiv/intdivrestoring.sv @@ -33,7 +33,8 @@ module intdivrestoring ( input logic StallM, input logic DivSignedE, W64E, input logic DivE, - input logic [`XLEN-1:0] SrcAE, SrcBE, + //input logic [`XLEN-1:0] SrcAE, SrcBE, + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B output logic DivBusyE, output logic [`XLEN-1:0] QuotM, RemM ); @@ -61,11 +62,11 @@ module intdivrestoring ( // Handle sign extension for W-type instructions generate if (`XLEN == 64) begin // RV64 has W-type instructions - mux2 #(`XLEN) xinmux(SrcAE, {SrcAE[31:0], 32'b0}, W64E, XinE); - mux2 #(`XLEN) dinmux(SrcBE, {{32{SrcBE[31]&DivSignedE}}, SrcBE[31:0]}, W64E, DinE); + mux2 #(`XLEN) xinmux(ForwardedSrcAE, {ForwardedSrcAE[31:0], 32'b0}, W64E, XinE); + mux2 #(`XLEN) dinmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31]&DivSignedE}}, ForwardedSrcBE[31:0]}, W64E, DinE); end else begin // RV32 has no W-type instructions - assign XinE = SrcAE; - assign DinE = SrcBE; + assign XinE = ForwardedSrcAE; + assign DinE = ForwardedSrcBE; end endgenerate @@ -79,7 +80,7 @@ module intdivrestoring ( neg #(`XLEN) negd(DinE, DnE); mux2 #(`XLEN) dabsmux(DnE, DinE, SignDE, DAbsBE); // take absolute value for signed operations, and negate for subtraction setp neg #(`XLEN) negx(XinE, XnE); - mux3 #(`XLEN) xabsmux(XinE, XnE, SrcAE, {Div0E, SignXE}, XInitE); // take absolute value for signed operations, or keep original value for divide by 0 + mux3 #(`XLEN) xabsmux(XinE, XnE, ForwardedSrcAE, {Div0E, SignXE}, XInitE); // take absolute value for signed operations, or keep original value for divide by 0 // initialization multiplexers on first cycle of operation mux2 #(`XLEN) wmux(WM[`DIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNextE); diff --git a/wally-pipelined/src/muldiv/mul.sv b/wally-pipelined/src/muldiv/mul.sv index dee645d3..e1174a9c 100644 --- a/wally-pipelined/src/muldiv/mul.sv +++ b/wally-pipelined/src/muldiv/mul.sv @@ -29,7 +29,8 @@ module mul ( // Execute Stage interface input logic clk, reset, input logic StallM, FlushM, - input logic [`XLEN-1:0] SrcAE, SrcBE, + // input logic [`XLEN-1:0] SrcAE, SrcBE, + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic [2:0] Funct3E, output logic [`XLEN*2-1:0] ProdM ); @@ -59,12 +60,12 @@ module mul ( // Execute Stage: Compute partial products ////////////////////////////// - assign Aprime = {1'b0, SrcAE[`XLEN-2:0]}; - assign Bprime = {1'b0, SrcBE[`XLEN-2:0]}; + assign Aprime = {1'b0, ForwardedSrcAE[`XLEN-2:0]}; + assign Bprime = {1'b0, ForwardedSrcBE[`XLEN-2:0]}; redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E)); - assign PA = {(`XLEN-1){SrcAE[`XLEN-1]}} & SrcBE[`XLEN-2:0]; - assign PB = {(`XLEN-1){SrcBE[`XLEN-1]}} & SrcAE[`XLEN-2:0]; - assign PP = SrcAE[`XLEN-1] & SrcBE[`XLEN-1]; + assign PA = {(`XLEN-1){ForwardedSrcAE[`XLEN-1]}} & ForwardedSrcBE[`XLEN-2:0]; + assign PB = {(`XLEN-1){ForwardedSrcBE[`XLEN-1]}} & ForwardedSrcAE[`XLEN-2:0]; + assign PP = ForwardedSrcAE[`XLEN-1] & ForwardedSrcBE[`XLEN-1]; // flavor of multiplication assign MULH = (Funct3E == 3'b001); @@ -88,6 +89,6 @@ module mul ( flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M); flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M); - assign ProdM = PP0M + PP1M + PP2M + PP3M + PP4M; //SrcAE * SrcBE; + assign ProdM = PP0M + PP1M + PP2M + PP3M + PP4M; //ForwardedSrcAE * ForwardedSrcBE; endmodule diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv index a98fb4f0..260167e8 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -28,7 +28,8 @@ module muldiv ( input logic clk, reset, // Execute Stage interface - input logic [`XLEN-1:0] SrcAE, SrcBE, + // input logic [`XLEN-1:0] SrcAE, SrcBE, + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic [2:0] Funct3E, Funct3M, input logic MulDivE, W64E, // Writeback stage @@ -58,7 +59,7 @@ module muldiv ( assign DivE = MulDivE & Funct3E[2]; assign DivSignedE = ~Funct3E[0]; intdivrestoring div(.clk, .reset, .StallM, - .DivSignedE, .W64E, .DivE, .SrcAE, .SrcBE, .DivBusyE, .QuotM, .RemM); + .DivSignedE, .W64E, .DivE, .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM); // Result multiplexer always_comb diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index ede4460e..1cecad7c 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -59,7 +59,7 @@ module wallypipelinedhart ( logic CSRReadM, CSRWriteM, PrivilegedM; logic [1:0] AtomicE; logic [1:0] AtomicM; - logic [`XLEN-1:0] SrcAE, SrcBE; + logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE, SrcBE; logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; // logic [31:0] InstrF; From 38437c664ec2f4270c0fee8315e8e868596098dd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 17 Nov 2021 12:17:56 -0800 Subject: [PATCH 5/7] root level makefile added --- Makefile | 26 ++++++++++++++++++++++++++ wally-pipelined/regression/Makefile | 6 +++--- 2 files changed, 29 insertions(+), 3 deletions(-) create mode 100644 Makefile diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..670409b3 --- /dev/null +++ b/Makefile @@ -0,0 +1,26 @@ +make all: submodules other +submodules: addins/riscv-isa-sim addins/riscv-arch-test + cd addins;git init; git submodule add https://github.com/riscv-non-isa/riscv-arch-test; git submodule add https://github.com/riscv-software-src/riscv-isa-sim + git submodule update --init --recursive + +other: + cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F + cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D + sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include + sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D/Makefile.include +ifneq ("$(wildcard $(addins/riscv-isa-sim/build/.*))",) +else + mkdir addins/riscv-isa-sim/build +endif + cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin + make -C addins/riscv-isa-sim/ + sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include + echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include + make -C tests/wally-riscv-arch-test + make -C tests/wally-riscv-arch-test XLEN=32 + cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf + make -C wally-pipelined/regression + + + + diff --git a/wally-pipelined/regression/Makefile b/wally-pipelined/regression/Makefile index cdebb5c0..ad6e427d 100644 --- a/wally-pipelined/regression/Makefile +++ b/wally-pipelined/regression/Makefile @@ -1,6 +1,6 @@ make all: - make ../../tests/imperas-riscv-tests/ - make ../../tests/wally-riscv-arch-test/ - make XLEN=32 ../../tests/wally-riscv-arch-test/ + make -C ../../tests/imperas-riscv-tests/ + make -C ../../tests/wally-riscv-arch-test/ + make -C XLEN=32 ../../tests/wally-riscv-arch-test/ exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh From 70a84b56c8652b57898e14ecfabebc14569358b4 Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Wed, 17 Nov 2021 12:39:05 -0800 Subject: [PATCH 6/7] Updated IFU variable naming for clarity --- .../src/wally/wallypipelinedhart.sv | 47 ++++++++++++------- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 1cecad7c..439a764b 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -155,26 +155,41 @@ module wallypipelinedhart ( ifu ifu( - .clk, .reset, - .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, - .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, .InstrReadF, .ICacheStallF, + .clk, .reset, + .StallF, .StallD, .StallE, .StallM, .StallW, + .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, + + // Fetch + .InstrInF(InstrRData), .InstrAckF, .PCF, .InstrPAdrF, + .InstrReadF, .ICacheStallF, + + // Execute .PCLinkE, .PCSrcE, .PCTargetE, .PCE, .BPPredWrongE, - .RetM, .TrapM, - .PrivilegedNextPCM, .InvalidateICacheM, - .InstrD, .InstrM, - .PCM, .InstrClassM, - .BPPredDirWrongM,.BTBPredPCWrongM,.RASPredPCWrongM, .BPPredClassNonCFIWrongM, - .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, .IllegalIEUInstrFaultD, - .InstrMisalignedFaultM, .InstrMisalignedAdrM, + + // Mem + .RetM, .TrapM, .PrivilegedNextPCM, .InvalidateICacheM, + .InstrD, .InstrM, . PCM, .InstrClassM, .BPPredDirWrongM, + .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, + + // Writeback + + // output logic + // Faults + .IllegalBaseInstrFaultD, .ITLBInstrPageFaultF, + .IllegalIEUInstrFaultD, .InstrMisalignedFaultM, + .InstrMisalignedAdrM, + + // mmu management .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, - .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, - .ITLBWriteF, .ITLBFlushF, - .WalkerInstrPageFaultF, - .ITLBMissF, - .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, + .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, + .STATUS_MPP, .ITLBWriteF, .ITLBFlushF, + .WalkerInstrPageFaultF, .ITLBMissF, + + // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H + .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF + ); // instruction fetch unit: PC, branch prediction, instruction cache From b63c0f35d10768d52266a9cd69177d85f4cc2a28 Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Wed, 17 Nov 2021 13:24:28 -0800 Subject: [PATCH 7/7] ieu variable naming changed for clarity --- .../src/wally/wallypipelinedhart.sv | 38 ++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 439a764b..523c0953 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -194,7 +194,43 @@ module wallypipelinedhart ( ); // instruction fetch unit: PC, branch prediction, instruction cache - ieu ieu(.*); // integer execution unit: integer register file, datapath and controller + ieu ieu( + .clk, .reset, + + // Decode Stage interface + .InstrD, .IllegalIEUInstrFaultD, + .IllegalBaseInstrFaultD, + + // Execute Stage interface + .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE, + .FWriteDataE, .PCTargetE, .MulDivE, .W64E, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B + .SrcAE, .SrcBE, .FWriteIntM, + + // Memory stage interface + .SquashSCW, // from LSU + .MemRWM, // read/write control goes to LSU + .AtomicE, // atomic control goes to LSU + .AtomicM, // atomic control goes to LSU + .MemAdrM, .MemAdrE, .WriteDataM, // Address and write data to LSU + .Funct3M, // size and signedness to LSU + .SrcAM, // to privilege and fpu + .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, + + // Writeback stage + .CSRReadValW, .ReadDataM, .MulDivResultW, + .FWriteIntW, .RdW, .ReadDataW, + .InstrValidM, + + // hazards + .StallD, .StallE, .StallM, .StallW, + .FlushD, .FlushE, .FlushM, .FlushW, + .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD, + .PCSrcE, + .CSRReadM, .CSRWriteM, .PrivilegedM, + .CSRWritePendingDEM, .StoreStallD + + ); // integer execution unit: integer register file, datapath and controller lsu lsu(.clk(clk), .reset(reset),