From 755e2e5771b7ca1cb5b0af2c4770f6310473bf41 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 8 Apr 2021 14:28:01 -0400 Subject: [PATCH 1/7] merge testbench --- .../regression/wally-peripherals.do | 43 -- wally-pipelined/regression/wally-pipelined.do | 10 +- .../regression/wave-dos/peripheral-waves.do | 19 - .../testbench/testbench-imperas.sv | 603 +++++++++--------- 4 files changed, 313 insertions(+), 362 deletions(-) delete mode 100644 wally-pipelined/regression/wally-peripherals.do diff --git a/wally-pipelined/regression/wally-peripherals.do b/wally-pipelined/regression/wally-peripherals.do deleted file mode 100644 index 83ad02d0..00000000 --- a/wally-pipelined/regression/wally-peripherals.do +++ /dev/null @@ -1,43 +0,0 @@ -# wally-peripherals.do -# -# Created by Ben Bracker (bbracker@hmc.edu) on 11 Feb. 2021 -# -# Based on wally-pipelined.do by -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! - -# Use this wally-pipelined.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -# That said, I don't think there are any peripherals that use anything but rv64i just yet. -switch $argc { - 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-peripherals.sv ../src/*/*.sv -suppress 2583} - 1 {vlog +incdir+$1 ../testbench/testbench-peripherals.sv ../src/*/*.sv -suppress 2583} -} -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt +acc work.testbench -o workopt -vsim workopt - - -view wave -do wave-dos/peripheral-waves.do diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index a5041005..7f08e56b 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -38,17 +38,15 @@ switch $argc { vopt +acc work.testbench -o workopt vsim workopt - view wave - -- display input and output signals as hexidecimal values -do ./wave-dos/ahb-waves.do +do ./wave-dos/peripheral-waves.do -- Set Wave Output Items TreeUpdate [SetDefaultTree] WaveRestoreZoom {0 ps} {100 ps} configure wave -namecolwidth 250 -configure wave -valuecolwidth 140 +configure wave -valuecolwidth 120 configure wave -justifyvalue left configure wave -signalnamewidth 0 configure wave -snapdistance 10 @@ -58,6 +56,8 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -#run 4100 +#run 5000 run -all #quit +noview ../testbench/testbench-imperas.sv +view wave diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do index c156be93..b635292d 100644 --- a/wally-pipelined/regression/wave-dos/peripheral-waves.do +++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do @@ -71,22 +71,3 @@ add wave -divider # everything else add wave -hex -r /testbench/* --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 120 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal - --- Run the Simulation -#run 5000 -run -all -#quit -noview ../testbench/testbench-peripherals.sv -view wave \ No newline at end of file diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 0cc7845a..4c9b46ad 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -29,6 +29,7 @@ module testbench(); parameter DEBUG = 0; parameter TESTSBP = 0; + parameter TESTSPERIPH = 1; logic clk; logic reset; @@ -42,314 +43,321 @@ module testbench(); logic [`XLEN-1:0] meminit; string tests32mmu[] = '{ - "rv32mmu/WALLY-VIRTUALMEMORY", "5000" + "rv32mmu/WALLY-VIRTUALMEMORY", "5000" }; string tests64mmu[] = '{ - "rv64mmu/WALLY-VIRTUALMEMORY", "5000" + "rv64mmu/WALLY-VIRTUALMEMORY", "5000" }; string tests64f[] = '{ - "rv64f/I-FADD-S-01", "2000", - "rv64f/I-FCLASS-S-01", "2000" + "rv64f/I-FADD-S-01", "2000", + "rv64f/I-FCLASS-S-01", "2000" }; string tests64a[] = '{ - "rv64a/WALLY-AMO", "2110", - "rv64a/WALLY-LRSC", "2110" + "rv64a/WALLY-AMO", "2110", + "rv64a/WALLY-LRSC", "2110" }; + string tests64m[] = '{ - "rv64m/I-MUL-01", "3000", - "rv64m/I-MULH-01", "3000", - "rv64m/I-MULHSU-01", "3000", - "rv64m/I-MULHU-01", "3000", - "rv64m/I-MULW-01", "3000" -// "rv64m/I-DIV-01", "3000", -// "rv64m/I-DIVU-01", "3000" - // "rv64m/I-DIVUW-01", "3000", - // "rv64m/I-DIVW-01", "3000", -// "rv64m/I-REM-01", "3000", -// "rv64m/I-REMU-01", "3000", -// "rv64m/I-REMUW-01", "3000", -// "rv64m/I-REMW-01", "3000" + "rv64m/I-MUL-01", "3000", + "rv64m/I-MULH-01", "3000", + "rv64m/I-MULHSU-01", "3000", + "rv64m/I-MULHU-01", "3000", + "rv64m/I-MULW-01", "3000" + //"rv64m/I-DIV-01", "3000", + //"rv64m/I-DIVU-01", "3000" + //"rv64m/I-DIVUW-01", "3000", + //"rv64m/I-DIVW-01", "3000", + //"rv64m/I-REM-01", "3000", + //"rv64m/I-REMU-01", "3000", + //"rv64m/I-REMUW-01", "3000", + //"rv64m/I-REMW-01", "3000" }; + string tests64ic[] = '{ - "rv64ic/I-C-ADD-01", "3000", - "rv64ic/I-C-ADDI-01", "3000", - "rv64ic/I-C-ADDIW-01", "3000", - "rv64ic/I-C-ADDW-01", "3000", - "rv64ic/I-C-AND-01", "3000", - "rv64ic/I-C-ANDI-01", "3000", - "rv64ic/I-C-BEQZ-01", "3000", - "rv64ic/I-C-BNEZ-01", "3000", - "rv64ic/I-C-EBREAK-01", "2000", - "rv64ic/I-C-J-01", "3000", - "rv64ic/I-C-JALR-01", "4000", - "rv64ic/I-C-JR-01", "4000", - "rv64ic/I-C-LD-01", "3420", - "rv64ic/I-C-LDSP-01", "3420", - "rv64ic/I-C-LI-01", "3000", - "rv64ic/I-C-LUI-01", "2000", - "rv64ic/I-C-LW-01", "3110", - "rv64ic/I-C-LWSP-01", "3110", - "rv64ic/I-C-MV-01", "3000", - "rv64ic/I-C-NOP-01", "2000", - "rv64ic/I-C-OR-01", "3000", - "rv64ic/I-C-SD-01", "3000", - "rv64ic/I-C-SDSP-01", "3000", - "rv64ic/I-C-SLLI-01", "3000", - "rv64ic/I-C-SRAI-01", "3000", - "rv64ic/I-C-SRLI-01", "3000", - "rv64ic/I-C-SUB-01", "3000", - "rv64ic/I-C-SUBW-01", "3000", - "rv64ic/I-C-SW-01", "3000", - "rv64ic/I-C-SWSP-01", "3000", - "rv64ic/I-C-XOR-01", "3000" + "rv64ic/I-C-ADD-01", "3000", + "rv64ic/I-C-ADDI-01", "3000", + "rv64ic/I-C-ADDIW-01", "3000", + "rv64ic/I-C-ADDW-01", "3000", + "rv64ic/I-C-AND-01", "3000", + "rv64ic/I-C-ANDI-01", "3000", + "rv64ic/I-C-BEQZ-01", "3000", + "rv64ic/I-C-BNEZ-01", "3000", + "rv64ic/I-C-EBREAK-01", "2000", + "rv64ic/I-C-J-01", "3000", + "rv64ic/I-C-JALR-01", "4000", + "rv64ic/I-C-JR-01", "4000", + "rv64ic/I-C-LD-01", "3420", + "rv64ic/I-C-LDSP-01", "3420", + "rv64ic/I-C-LI-01", "3000", + "rv64ic/I-C-LUI-01", "2000", + "rv64ic/I-C-LW-01", "3110", + "rv64ic/I-C-LWSP-01", "3110", + "rv64ic/I-C-MV-01", "3000", + "rv64ic/I-C-NOP-01", "2000", + "rv64ic/I-C-OR-01", "3000", + "rv64ic/I-C-SD-01", "3000", + "rv64ic/I-C-SDSP-01", "3000", + "rv64ic/I-C-SLLI-01", "3000", + "rv64ic/I-C-SRAI-01", "3000", + "rv64ic/I-C-SRLI-01", "3000", + "rv64ic/I-C-SUB-01", "3000", + "rv64ic/I-C-SUBW-01", "3000", + "rv64ic/I-C-SW-01", "3000", + "rv64ic/I-C-SWSP-01", "3000", + "rv64ic/I-C-XOR-01", "3000" }; -string tests64iNOc[] = { - "rv64i/I-MISALIGN_JMP-01","2000" - }; - string tests64i[] = '{ - "rv64i/I-ADD-01", "3000", - "rv64i/I-ADDI-01", "3000", - "rv64i/I-ADDIW-01", "3000", - "rv64i/I-ADDW-01", "3000", - "rv64i/I-AND-01", "3000", - "rv64i/I-ANDI-01", "3000", - "rv64i/I-AUIPC-01", "3000", - "rv64i/I-BEQ-01", "4000", - "rv64i/I-BGE-01", "4000", - "rv64i/I-BGEU-01", "4000", - "rv64i/I-BLT-01", "4000", - "rv64i/I-BLTU-01", "4000", - "rv64i/I-BNE-01", "4000", - "rv64i/I-DELAY_SLOTS-01", "2000", - "rv64i/I-EBREAK-01", "2000", - "rv64i/I-ECALL-01", "2000", - "rv64i/I-ENDIANESS-01", "2010", - "rv64i/I-IO-01", "2050", - "rv64i/I-JAL-01", "3000", - "rv64i/I-JALR-01", "4000", - "rv64i/I-LB-01", "4020", - "rv64i/I-LBU-01", "4020", - "rv64i/I-LD-01", "4420", - "rv64i/I-LH-01", "4050", - "rv64i/I-LHU-01", "4050", - "rv64i/I-LUI-01", "2000", - "rv64i/I-LW-01", "4110", - "rv64i/I-LWU-01", "4110", - "rv64i/I-MISALIGN_LDST-01", "2010", - "rv64i/I-NOP-01", "2000", - "rv64i/I-OR-01", "3000", - "rv64i/I-ORI-01", "3000", - "rv64i/I-RF_size-01", "2000", - "rv64i/I-RF_width-01", "2000", - "rv64i/I-RF_x0-01", "2010", - "rv64i/I-SB-01", "4000", - "rv64i/I-SD-01", "4000", - "rv64i/I-SH-01", "4000", - "rv64i/I-SLL-01", "3000", - "rv64i/I-SLLI-01", "3000", - "rv64i/I-SLLIW-01", "3000", - "rv64i/I-SLLW-01", "3000", - "rv64i/I-SLT-01", "3000", - "rv64i/I-SLTI-01", "3000", - "rv64i/I-SLTIU-01", "3000", - "rv64i/I-SLTU-01", "3000", - "rv64i/I-SRA-01", "3000", - "rv64i/I-SRAI-01", "3000", - "rv64i/I-SRAIW-01", "3000", - "rv64i/I-SRAW-01", "3000", - "rv64i/I-SRL-01", "3000", - "rv64i/I-SRLI-01", "3000", - "rv64i/I-SRLIW-01", "3000", - "rv64i/I-SRLW-01", "3000", - "rv64i/I-SUB-01", "3000", - "rv64i/I-SUBW-01", "3000", - "rv64i/I-SW-01", "4000", - "rv64i/I-XOR-01", "3000", - "rv64i/I-XORI-01", "3000", - "rv64i/WALLY-ADD", "4000", - "rv64i/WALLY-SUB", "4000", - "rv64i/WALLY-ADDI", "3000", - "rv64i/WALLY-ANDI", "3000", - "rv64i/WALLY-ORI", "3000", - "rv64i/WALLY-XORI", "3000", - "rv64i/WALLY-SLTI", "3000", - "rv64i/WALLY-SLTIU", "3000", - "rv64i/WALLY-SLLI", "3000", - "rv64i/WALLY-SRLI", "3000", - "rv64i/WALLY-SRAI", "3000", - "rv64i/WALLY-LOAD", "11bf0", - "rv64i/WALLY-JAL", "4000", - "rv64i/WALLY-JALR", "3000", - "rv64i/WALLY-STORE", "3000", - "rv64i/WALLY-ADDIW", "3000", - "rv64i/WALLY-SLLIW", "3000", - "rv64i/WALLY-SRLIW", "3000", - "rv64i/WALLY-SRAIW", "3000", - "rv64i/WALLY-ADDW", "4000", - "rv64i/WALLY-SUBW", "4000", - "rv64i/WALLY-SLLW", "3000", - "rv64i/WALLY-SRLW", "3000", - "rv64i/WALLY-SRAW", "3000", - "rv64i/WALLY-BEQ" ,"5000", - "rv64i/WALLY-BNE", "5000 ", - "rv64i/WALLY-BLTU", "5000 ", - "rv64i/WALLY-BLT", "5000", - "rv64i/WALLY-BGE", "5000 ", - "rv64i/WALLY-BGEU", "5000 ", - "rv64i/WALLY-CSRRW", "4000", - "rv64i/WALLY-CSRRS", "4000", - "rv64i/WALLY-CSRRC", "5000", - "rv64i/WALLY-CSRRWI", "4000", - "rv64i/WALLY-CSRRSI", "4000", - "rv64i/WALLY-CSRRCI", "4000" + string tests64iNOc[] = { + "rv64i/I-MISALIGN_JMP-01","2000" }; + + string tests64i[] = '{ + "rv64i/I-ADD-01", "3000", + "rv64i/I-ADDI-01", "3000", + "rv64i/I-ADDIW-01", "3000", + "rv64i/I-ADDW-01", "3000", + "rv64i/I-AND-01", "3000", + "rv64i/I-ANDI-01", "3000", + "rv64i/I-AUIPC-01", "3000", + "rv64i/I-BEQ-01", "4000", + "rv64i/I-BGE-01", "4000", + "rv64i/I-BGEU-01", "4000", + "rv64i/I-BLT-01", "4000", + "rv64i/I-BLTU-01", "4000", + "rv64i/I-BNE-01", "4000", + "rv64i/I-DELAY_SLOTS-01", "2000", + "rv64i/I-EBREAK-01", "2000", + "rv64i/I-ECALL-01", "2000", + "rv64i/I-ENDIANESS-01", "2010", + "rv64i/I-IO-01", "2050", + "rv64i/I-JAL-01", "3000", + "rv64i/I-JALR-01", "4000", + "rv64i/I-LB-01", "4020", + "rv64i/I-LBU-01", "4020", + "rv64i/I-LD-01", "4420", + "rv64i/I-LH-01", "4050", + "rv64i/I-LHU-01", "4050", + "rv64i/I-LUI-01", "2000", + "rv64i/I-LW-01", "4110", + "rv64i/I-LWU-01", "4110", + "rv64i/I-MISALIGN_LDST-01", "2010", + "rv64i/I-NOP-01", "2000", + "rv64i/I-OR-01", "3000", + "rv64i/I-ORI-01", "3000", + "rv64i/I-RF_size-01", "2000", + "rv64i/I-RF_width-01", "2000", + "rv64i/I-RF_x0-01", "2010", + "rv64i/I-SB-01", "4000", + "rv64i/I-SD-01", "4000", + "rv64i/I-SH-01", "4000", + "rv64i/I-SLL-01", "3000", + "rv64i/I-SLLI-01", "3000", + "rv64i/I-SLLIW-01", "3000", + "rv64i/I-SLLW-01", "3000", + "rv64i/I-SLT-01", "3000", + "rv64i/I-SLTI-01", "3000", + "rv64i/I-SLTIU-01", "3000", + "rv64i/I-SLTU-01", "3000", + "rv64i/I-SRA-01", "3000", + "rv64i/I-SRAI-01", "3000", + "rv64i/I-SRAIW-01", "3000", + "rv64i/I-SRAW-01", "3000", + "rv64i/I-SRL-01", "3000", + "rv64i/I-SRLI-01", "3000", + "rv64i/I-SRLIW-01", "3000", + "rv64i/I-SRLW-01", "3000", + "rv64i/I-SUB-01", "3000", + "rv64i/I-SUBW-01", "3000", + "rv64i/I-SW-01", "4000", + "rv64i/I-XOR-01", "3000", + "rv64i/I-XORI-01", "3000", + "rv64i/WALLY-ADD", "4000", + "rv64i/WALLY-SUB", "4000", + "rv64i/WALLY-ADDI", "3000", + "rv64i/WALLY-ANDI", "3000", + "rv64i/WALLY-ORI", "3000", + "rv64i/WALLY-XORI", "3000", + "rv64i/WALLY-SLTI", "3000", + "rv64i/WALLY-SLTIU", "3000", + "rv64i/WALLY-SLLI", "3000", + "rv64i/WALLY-SRLI", "3000", + "rv64i/WALLY-SRAI", "3000", + "rv64i/WALLY-LOAD", "11bf0", + "rv64i/WALLY-JAL", "4000", + "rv64i/WALLY-JALR", "3000", + "rv64i/WALLY-STORE", "3000", + "rv64i/WALLY-ADDIW", "3000", + "rv64i/WALLY-SLLIW", "3000", + "rv64i/WALLY-SRLIW", "3000", + "rv64i/WALLY-SRAIW", "3000", + "rv64i/WALLY-ADDW", "4000", + "rv64i/WALLY-SUBW", "4000", + "rv64i/WALLY-SLLW", "3000", + "rv64i/WALLY-SRLW", "3000", + "rv64i/WALLY-SRAW", "3000", + "rv64i/WALLY-BEQ" ,"5000", + "rv64i/WALLY-BNE", "5000 ", + "rv64i/WALLY-BLTU", "5000 ", + "rv64i/WALLY-BLT", "5000", + "rv64i/WALLY-BGE", "5000 ", + "rv64i/WALLY-BGEU", "5000 ", + "rv64i/WALLY-CSRRW", "4000", + "rv64i/WALLY-CSRRS", "4000", + "rv64i/WALLY-CSRRC", "5000", + "rv64i/WALLY-CSRRWI", "4000", + "rv64i/WALLY-CSRRSI", "4000", + "rv64i/WALLY-CSRRCI", "4000" + }; + string tests32a[] = '{ - "rv64a/WALLY-AMO", "2110", - "rv64a/WALLY-LRSC", "2110" + "rv64a/WALLY-AMO", "2110", + "rv64a/WALLY-LRSC", "2110" }; - string tests32m[] = '{ - "rv32m/I-MUL-01", "2000", - "rv32m/I-MULH-01", "2000", - "rv32m/I-MULHSU-01", "2000", - "rv32m/I-MULHU-01", "2000" -// "rv32m/I-DIV-01", "2000", -// "rv32m/I-DIVU-01", "2000", -// "rv32m/I-REM-01", "2000", -// "rv32m/I-REMU-01", "2000" - }; -string tests32ic[] = '{ - "rv32ic/I-C-ADD-01", "2000", - "rv32ic/I-C-ADDI-01", "2000", - "rv32ic/I-C-AND-01", "2000", - "rv32ic/I-C-ANDI-01", "2000", - "rv32ic/I-C-BEQZ-01", "2000", - "rv32ic/I-C-BNEZ-01", "2000", - "rv32ic/I-C-EBREAK-01", "2000", - "rv32ic/I-C-J-01", "2000", - "rv32ic/I-C-JALR-01", "3000", - "rv32ic/I-C-JR-01", "3000", - "rv32ic/I-C-LI-01", "2000", - "rv32ic/I-C-LUI-01", "2000", - "rv32ic/I-C-LW-01", "2110", - "rv32ic/I-C-LWSP-01", "2110", - "rv32ic/I-C-MV-01", "2000", - "rv32ic/I-C-NOP-01", "2000", - "rv32ic/I-C-OR-01", "2000", - "rv32ic/I-C-SLLI-01", "2000", - "rv32ic/I-C-SRAI-01", "2000", - "rv32ic/I-C-SRLI-01", "2000", - "rv32ic/I-C-SUB-01", "2000", - "rv32ic/I-C-SW-01", "2000", - "rv32ic/I-C-SWSP-01", "2000", - "rv32ic/I-C-XOR-01", "2000" -}; -string tests32iNOc[] = { - "rv32i/I-MISALIGN_JMP-01","2000" -}; -string tests32i[] = { - "rv32i/I-ADD-01", "2000", - "rv32i/I-ADDI-01","2000", - "rv32i/I-AND-01","2000", - "rv32i/I-ANDI-01","2000", - "rv32i/I-AUIPC-01","2000", - "rv32i/I-BEQ-01","3000", - "rv32i/I-BGE-01","3000", - "rv32i/I-BGEU-01","3000", - "rv32i/I-BLT-01","3000", - "rv32i/I-BLTU-01","3000", - "rv32i/I-BNE-01","3000", - "rv32i/I-DELAY_SLOTS-01","2000", - "rv32i/I-EBREAK-01","2000", - "rv32i/I-ECALL-01","2000", - "rv32i/I-ENDIANESS-01","2010", - "rv32i/I-IO-01","2030", - "rv32i/I-JAL-01","3000", - "rv32i/I-JALR-01","3000", - "rv32i/I-LB-01","3020", - "rv32i/I-LBU-01","3020", - "rv32i/I-LH-01","3050", - "rv32i/I-LHU-01","3050", - "rv32i/I-LUI-01","2000", - "rv32i/I-LW-01","3110", - "rv32i/I-MISALIGN_LDST-01","2010", - "rv32i/I-NOP-01","2000", - "rv32i/I-OR-01","2000", - "rv32i/I-ORI-01","2000", - "rv32i/I-RF_size-01","2000", - "rv32i/I-RF_width-01","2000", - "rv32i/I-RF_x0-01","2010", - "rv32i/I-SB-01","3000", - "rv32i/I-SH-01","3000", - "rv32i/I-SLL-01","2000", - "rv32i/I-SLLI-01","2000", - "rv32i/I-SLT-01","2000", - "rv32i/I-SLTI-01","2000", - "rv32i/I-SLTIU-01","2000", - "rv32i/I-SLTU-01","2000", - "rv32i/I-SRA-01","2000", - "rv32i/I-SRAI-01","2000", - "rv32i/I-SRL-01","2000", - "rv32i/I-SRLI-01","2000", - "rv32i/I-SUB-01","2000", - "rv32i/I-SW-01","3000", - "rv32i/I-XOR-01","2000", - "rv32i/I-XORI-01","2000", - "rv32i/WALLY-ADD", "3000", - "rv32i/WALLY-SUB", "3000", - "rv32i/WALLY-ADDI", "2000", - "rv32i/WALLY-ANDI", "2000", - "rv32i/WALLY-ORI", "2000", - "rv32i/WALLY-XORI", "2000", - "rv32i/WALLY-SLTI", "2000", - "rv32i/WALLY-SLTIU", "2000", - "rv32i/WALLY-SLLI", "2000", - "rv32i/WALLY-SRLI", "2000", - "rv32i/WALLY-SRAI", "2000", - "rv32i/WALLY-LOAD", "11c00", - "rv32i/WALLY-SUB", "3000", - "rv32i/WALLY-STORE", "2000", - "rv32i/WALLY-JAL", "3000", - "rv32i/WALLY-JALR", "2000", - "rv32i/WALLY-BEQ" ,"4000", - "rv32i/WALLY-BNE", "4000 ", - "rv32i/WALLY-BLTU", "4000 ", - "rv32i/WALLY-BLT", "4000", - "rv32i/WALLY-BGE", "4000 ", - "rv32i/WALLY-BGEU", "4000 ", - "rv32i/WALLY-CSRRW", "3000", - "rv32i/WALLY-CSRRS", "3000", - "rv32i/WALLY-CSRRC", "4000", - "rv32i/WALLY-CSRRWI", "3000", - "rv32i/WALLY-CSRRSI", "3000", - "rv32i/WALLY-CSRRCI", "3000" -}; + string tests32m[] = '{ + "rv32m/I-MUL-01", "2000", + "rv32m/I-MULH-01", "2000", + "rv32m/I-MULHSU-01", "2000", + "rv32m/I-MULHU-01", "2000" + //"rv32m/I-DIV-01", "2000", + //"rv32m/I-DIVU-01", "2000", + //"rv32m/I-REM-01", "2000", + //"rv32m/I-REMU-01", "2000" + }; + + string tests32ic[] = '{ + "rv32ic/I-C-ADD-01", "2000", + "rv32ic/I-C-ADDI-01", "2000", + "rv32ic/I-C-AND-01", "2000", + "rv32ic/I-C-ANDI-01", "2000", + "rv32ic/I-C-BEQZ-01", "2000", + "rv32ic/I-C-BNEZ-01", "2000", + "rv32ic/I-C-EBREAK-01", "2000", + "rv32ic/I-C-J-01", "2000", + "rv32ic/I-C-JALR-01", "3000", + "rv32ic/I-C-JR-01", "3000", + "rv32ic/I-C-LI-01", "2000", + "rv32ic/I-C-LUI-01", "2000", + "rv32ic/I-C-LW-01", "2110", + "rv32ic/I-C-LWSP-01", "2110", + "rv32ic/I-C-MV-01", "2000", + "rv32ic/I-C-NOP-01", "2000", + "rv32ic/I-C-OR-01", "2000", + "rv32ic/I-C-SLLI-01", "2000", + "rv32ic/I-C-SRAI-01", "2000", + "rv32ic/I-C-SRLI-01", "2000", + "rv32ic/I-C-SUB-01", "2000", + "rv32ic/I-C-SW-01", "2000", + "rv32ic/I-C-SWSP-01", "2000", + "rv32ic/I-C-XOR-01", "2000" + }; + + string tests32iNOc[] = { + "rv32i/I-MISALIGN_JMP-01","2000" + }; + + string tests32i[] = { + "rv32i/I-ADD-01", "2000", + "rv32i/I-ADDI-01","2000", + "rv32i/I-AND-01","2000", + "rv32i/I-ANDI-01","2000", + "rv32i/I-AUIPC-01","2000", + "rv32i/I-BEQ-01","3000", + "rv32i/I-BGE-01","3000", + "rv32i/I-BGEU-01","3000", + "rv32i/I-BLT-01","3000", + "rv32i/I-BLTU-01","3000", + "rv32i/I-BNE-01","3000", + "rv32i/I-DELAY_SLOTS-01","2000", + "rv32i/I-EBREAK-01","2000", + "rv32i/I-ECALL-01","2000", + "rv32i/I-ENDIANESS-01","2010", + "rv32i/I-IO-01","2030", + "rv32i/I-JAL-01","3000", + "rv32i/I-JALR-01","3000", + "rv32i/I-LB-01","3020", + "rv32i/I-LBU-01","3020", + "rv32i/I-LH-01","3050", + "rv32i/I-LHU-01","3050", + "rv32i/I-LUI-01","2000", + "rv32i/I-LW-01","3110", + "rv32i/I-MISALIGN_LDST-01","2010", + "rv32i/I-NOP-01","2000", + "rv32i/I-OR-01","2000", + "rv32i/I-ORI-01","2000", + "rv32i/I-RF_size-01","2000", + "rv32i/I-RF_width-01","2000", + "rv32i/I-RF_x0-01","2010", + "rv32i/I-SB-01","3000", + "rv32i/I-SH-01","3000", + "rv32i/I-SLL-01","2000", + "rv32i/I-SLLI-01","2000", + "rv32i/I-SLT-01","2000", + "rv32i/I-SLTI-01","2000", + "rv32i/I-SLTIU-01","2000", + "rv32i/I-SLTU-01","2000", + "rv32i/I-SRA-01","2000", + "rv32i/I-SRAI-01","2000", + "rv32i/I-SRL-01","2000", + "rv32i/I-SRLI-01","2000", + "rv32i/I-SUB-01","2000", + "rv32i/I-SW-01","3000", + "rv32i/I-XOR-01","2000", + "rv32i/I-XORI-01","2000", + "rv32i/WALLY-ADD", "3000", + "rv32i/WALLY-SUB", "3000", + "rv32i/WALLY-ADDI", "2000", + "rv32i/WALLY-ANDI", "2000", + "rv32i/WALLY-ORI", "2000", + "rv32i/WALLY-XORI", "2000", + "rv32i/WALLY-SLTI", "2000", + "rv32i/WALLY-SLTIU", "2000", + "rv32i/WALLY-SLLI", "2000", + "rv32i/WALLY-SRLI", "2000", + "rv32i/WALLY-SRAI", "2000", + "rv32i/WALLY-LOAD", "11c00", + "rv32i/WALLY-SUB", "3000", + "rv32i/WALLY-STORE", "2000", + "rv32i/WALLY-JAL", "3000", + "rv32i/WALLY-JALR", "2000", + "rv32i/WALLY-BEQ" ,"4000", + "rv32i/WALLY-BNE", "4000 ", + "rv32i/WALLY-BLTU", "4000 ", + "rv32i/WALLY-BLT", "4000", + "rv32i/WALLY-BGE", "4000 ", + "rv32i/WALLY-BGEU", "4000 ", + "rv32i/WALLY-CSRRW", "3000", + "rv32i/WALLY-CSRRS", "3000", + "rv32i/WALLY-CSRRC", "4000", + "rv32i/WALLY-CSRRWI", "3000", + "rv32i/WALLY-CSRRSI", "3000", + "rv32i/WALLY-CSRRCI", "3000" + }; string testsBP64[] = '{ - "rv64BP/reg-test", "10000" - }; + "rv64BP/reg-test", "10000" + }; - // string tests64p[] = '{ - // "rv64p/WALLY-CAUSE", "3000", - // "rv64p/WALLY-EPC", "3000", - // "rv64p/WALLY-TVAL", "3000" - // }; + string tests64p[] = '{ + "rv64p/WALLY-CAUSE", "3000", + "rv64p/WALLY-EPC", "3000", + "rv64p/WALLY-TVAL", "3000", + "rv64p/WALLY-MARCHID", "4000", + "rv64p/WALLY-MIMPID", "4000", + "rv64p/WALLY-MHARTID", "4000", + "rv64p/WALLY-MVENDORID", "4000" + }; - + string tests64periph[] = '{ + "rv64i-periph/WALLY-PLIC", "2000" + }; - string tests64p[] = '{ - "rv64p/WALLY-CAUSE", "3000", - "rv64p/WALLY-EPC", "3000", - "rv64p/WALLY-TVAL", "3000", - "rv64p/WALLY-MARCHID", "4000", - "rv64p/WALLY-MIMPID", "4000", - "rv64p/WALLY-MHARTID", "4000", - "rv64p/WALLY-MVENDORID", "4000" - }; + string tests32periph[] = '{ + "rv32i-periph/WALLY-PLIC", "2000" + }; @@ -374,9 +382,11 @@ string tests32i[] = { initial begin if (`XLEN == 64) begin // RV64 if (TESTSBP) begin - tests = testsBP64; + tests = testsBP64; + end if (TESTSPERIPH) begin + tests = tests64periph; end else begin - tests = {tests64i}; + tests = {tests64i,tests64periph}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; @@ -385,19 +395,22 @@ string tests32i[] = { if (`A_SUPPORTED) tests = {tests, tests64a}; if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end - // tests = {tests64a, tests}; + //tests = {tests64a, tests}; tests = {tests, tests64p}; end else begin // RV32 // *** add the 32 bit bp tests - tests = {tests32i}; - if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; - else tests = {tests, tests32iNOc}; - if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; - // if (`F_SUPPORTED) tests = {tests32f, tests}; - if (`A_SUPPORTED) tests = {tests, tests32a}; - if (`MEM_VIRTMEM) tests = {tests32mmu, tests}; + if (TESTSPERIPH) begin + tests = tests32periph; + end else begin + tests = {tests32i,tests32periph}; + if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; + else tests = {tests, tests32iNOc}; + if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m}; + // if (`F_SUPPORTED) tests = {tests32f, tests}; + if (`A_SUPPORTED) tests = {tests, tests32a}; + if (`MEM_VIRTMEM) tests = {tests32mmu, tests}; + end end - //tests = tests64p; end From 1ee8feffe50a07ccc8c16c26ef23dc81c7ecce17 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 8 Apr 2021 15:31:39 -0400 Subject: [PATCH 2/7] integrated peripheral testing into existing workflow --- wally-pipelined/testbench/testbench-imperas.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 4c9b46ad..67846e97 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -29,7 +29,7 @@ module testbench(); parameter DEBUG = 0; parameter TESTSBP = 0; - parameter TESTSPERIPH = 1; + parameter TESTSPERIPH = 0; // set to 0 for regression logic clk; logic reset; @@ -382,11 +382,11 @@ module testbench(); initial begin if (`XLEN == 64) begin // RV64 if (TESTSBP) begin - tests = testsBP64; + tests = {testsBP64,tests64p}; end if (TESTSPERIPH) begin tests = tests64periph; end else begin - tests = {tests64i,tests64periph}; + tests = {tests64i,tests64p,tests64periph}; if (`C_SUPPORTED) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; if (`M_SUPPORTED) tests = {tests, tests64m}; @@ -396,7 +396,7 @@ module testbench(); if (`MEM_VIRTMEM) tests = {tests64mmu, tests}; end //tests = {tests64a, tests}; - tests = {tests, tests64p}; + // tests = {tests, tests64p}; end else begin // RV32 // *** add the 32 bit bp tests if (TESTSPERIPH) begin From 99f2d24e05cae07a135f97cdcbe6c3b75a8c7a1f Mon Sep 17 00:00:00 2001 From: ushakya22 Date: Thu, 8 Apr 2021 17:53:39 -0400 Subject: [PATCH 3/7] Latest IE tests with timer interupts --- wally-pipelined/testgen/privileged/testgen-IE.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/testgen/privileged/testgen-IE.py b/wally-pipelined/testgen/privileged/testgen-IE.py index ef8a524c..b0b77b0c 100644 --- a/wally-pipelined/testgen/privileged/testgen-IE.py +++ b/wally-pipelined/testgen/privileged/testgen-IE.py @@ -251,7 +251,7 @@ def writeVectors(a, xlen, storecmd): ################################## # change these to suite your tests -tests = ["timerM", "timerS", "timerU", "softwareM", "softwareS", "softwareU"] +tests = ["timerM"] #, "timerS", "timerU", "softwareM", "softwareS", "softwareU"] author = "ushakya@hmc.edu" xlens = [64, 32] numrand = 100; From 35f8b4f74fb7dc697f7f30930877fd8f4896d7f5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 9 Apr 2021 10:56:31 -0500 Subject: [PATCH 4/7] Fixed minor bug in muldiv which corrects the lint error. --- wally-pipelined/src/muldiv/muldiv.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv index 9974dae0..c61b02c4 100644 --- a/wally-pipelined/src/muldiv/muldiv.sv +++ b/wally-pipelined/src/muldiv/muldiv.sv @@ -62,7 +62,7 @@ module muldiv ( // Divide // *** replace this clock gater - always @(~clk) begin + always @(negedge clk) begin enable_q <= ~StallM; end assign gclk = enable_q & clk; From 1018a106256078d227e0e403770d891655187e57 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Tue, 13 Apr 2021 11:27:12 -0500 Subject: [PATCH 5/7] Various code syntax changes to bring HDL to a synthesizable level --- .../{src => misc}/tlb_toy/tlb_testbench.sv | 0 .../{src => misc}/tlb_toy/tlb_toy.sv.OLD | 0 .../{src => misc}/tlb_toy/tlb_toy.tv | 0 wally-pipelined/src/cache/dmapped.sv | 16 +-- wally-pipelined/src/cache/line.sv | 2 +- wally-pipelined/src/ebu/pagetablewalker.sv | 113 +++++++++--------- wally-pipelined/src/fpu/fpu.sv | 16 ++- wally-pipelined/src/ifu/icache.sv | 10 +- wally-pipelined/src/mmu/cam_line.sv | 5 +- wally-pipelined/src/mmu/tlb.sv | 6 +- wally-pipelined/src/mmu/tlb_ram.sv | 2 +- wally-pipelined/src/mmu/tlb_rand.sv | 2 +- wally-pipelined/src/muldiv/div.sv | 66 ++++------ wally-pipelined/src/privileged/csrc.sv | 2 +- .../src/wally/wallypipelinedhart.sv | 1 + 15 files changed, 113 insertions(+), 128 deletions(-) rename wally-pipelined/{src => misc}/tlb_toy/tlb_testbench.sv (100%) rename wally-pipelined/{src => misc}/tlb_toy/tlb_toy.sv.OLD (100%) rename wally-pipelined/{src => misc}/tlb_toy/tlb_toy.tv (100%) diff --git a/wally-pipelined/src/tlb_toy/tlb_testbench.sv b/wally-pipelined/misc/tlb_toy/tlb_testbench.sv similarity index 100% rename from wally-pipelined/src/tlb_toy/tlb_testbench.sv rename to wally-pipelined/misc/tlb_toy/tlb_testbench.sv diff --git a/wally-pipelined/src/tlb_toy/tlb_toy.sv.OLD b/wally-pipelined/misc/tlb_toy/tlb_toy.sv.OLD similarity index 100% rename from wally-pipelined/src/tlb_toy/tlb_toy.sv.OLD rename to wally-pipelined/misc/tlb_toy/tlb_toy.sv.OLD diff --git a/wally-pipelined/src/tlb_toy/tlb_toy.tv b/wally-pipelined/misc/tlb_toy/tlb_toy.tv similarity index 100% rename from wally-pipelined/src/tlb_toy/tlb_toy.tv rename to wally-pipelined/misc/tlb_toy/tlb_toy.tv diff --git a/wally-pipelined/src/cache/dmapped.sv b/wally-pipelined/src/cache/dmapped.sv index 9a51737a..f9d2bc8e 100644 --- a/wally-pipelined/src/cache/dmapped.sv +++ b/wally-pipelined/src/cache/dmapped.sv @@ -59,13 +59,13 @@ module rodirectmappedmem #(parameter LINESIZE = 256, parameter NUMLINES = 512, p // Swizzle bits to get the offset, set, and tag out of the read and write addresses always_comb begin // Read address - assign WordSelect = ReadLowerAdr[OFFSETWIDTH-1:0]; - assign ReadPAdr = {ReadUpperPAdr, ReadLowerAdr}; - assign ReadSet = ReadPAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; - assign ReadTag = ReadPAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; + WordSelect = ReadLowerAdr[OFFSETWIDTH-1:0]; + ReadPAdr = {ReadUpperPAdr, ReadLowerAdr}; + ReadSet = ReadPAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; + ReadTag = ReadPAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; // Write address - assign WriteSet = WritePAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; - assign WriteTag = WritePAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; + WriteSet = WritePAdr[SETWIDTH+OFFSETWIDTH-1:OFFSETWIDTH]; + WriteTag = WritePAdr[`XLEN-1:SETWIDTH+OFFSETWIDTH]; end genvar i; @@ -85,8 +85,8 @@ module rodirectmappedmem #(parameter LINESIZE = 256, parameter NUMLINES = 512, p // Get the data and valid out of the lines always_comb begin - assign DataWord = LineOutputs[ReadSet]; - assign DataValid = ValidOutputs[ReadSet] & (TagOutputs[ReadSet] == ReadTag); + DataWord = LineOutputs[ReadSet]; + DataValid = ValidOutputs[ReadSet] & (TagOutputs[ReadSet] == ReadTag); end endmodule diff --git a/wally-pipelined/src/cache/line.sv b/wally-pipelined/src/cache/line.sv index e498d073..8b6e5e46 100644 --- a/wally-pipelined/src/cache/line.sv +++ b/wally-pipelined/src/cache/line.sv @@ -62,7 +62,7 @@ module rocacheline #(parameter LINESIZE = 256, parameter TAGSIZE = 32, parameter always_comb begin - assign DataWord = DataLinesOut[WordSelect[OFFSETSIZE-1:$clog2(WORDSIZE)]]; + DataWord = DataLinesOut[WordSelect[OFFSETSIZE-1:$clog2(WORDSIZE)]]; end endmodule diff --git a/wally-pipelined/src/ebu/pagetablewalker.sv b/wally-pipelined/src/ebu/pagetablewalker.sv index 83c1de84..357287aa 100644 --- a/wally-pipelined/src/ebu/pagetablewalker.sv +++ b/wally-pipelined/src/ebu/pagetablewalker.sv @@ -85,7 +85,7 @@ module pagetablewalker ( // Signals for direct, fake translations. Not part of the final Wally version. logic [`XLEN-1:0] DirectInstrPTE, DirectMemPTE; - logic [9:0] DirectPTEFlags = {2'b0, 8'b00001111}; + localparam DirectPTEFlags = {2'b0, 8'b00001111}; logic [`VPN_BITS-1:0] PCPageNumber, MemAdrPageNumber; @@ -133,17 +133,23 @@ module pagetablewalker ( assign PageTypeF = PageType; assign PageTypeM = PageType; + localparam IDLE = 3'h0; + localparam LEVEL1 = 3'h1; + localparam LEVEL0 = 3'h2; + localparam LEAF = 3'h3; + localparam FAULT = 3'h4; + localparam LEVEL2 = 3'h5; + + logic [2:0] WalkerState, NextWalkerState; + generate if (`XLEN == 32) begin logic [9:0] VPN1, VPN0; assign SvMode = SATP_REGW[31]; - typedef enum {IDLE, LEVEL1, LEVEL0, LEAF, FAULT} walker_statetype; - walker_statetype WalkerState, NextWalkerState; - // *** Do we need a synchronizer here for walker to talk to ahblite? - flopenl #(.TYPE(walker_statetype)) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(3) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); // State transition logic always_comb begin @@ -179,38 +185,38 @@ module pagetablewalker ( // Assign combinational outputs always_comb begin // default values - assign TranslationPAdr = '0; - assign PageTableEntry = '0; - assign PageType ='0; - assign MMUTranslationComplete = '0; - assign DTLBWriteM = '0; - assign ITLBWriteF = '0; - assign InstrPageFaultM = '0; - assign LoadPageFaultM = '0; - assign StorePageFaultM = '0; + TranslationPAdr = '0; + PageTableEntry = '0; + PageType ='0; + MMUTranslationComplete = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + InstrPageFaultM = '0; + LoadPageFaultM = '0; + StorePageFaultM = '0; case (NextWalkerState) LEVEL1: begin - assign TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; + TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00}; end LEVEL0: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; end LEAF: begin // Keep physical address alive to prevent HADDR dropping to 0 - assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - assign PageTableEntry = CurrentPTE; - assign PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; - assign MMUTranslationComplete = '1; - assign DTLBWriteM = DTLBMissM; - assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL1) ? 2'b01 : 2'b00; + MMUTranslationComplete = '1; + DTLBWriteM = DTLBMissM; + ITLBWriteF = ~DTLBMissM; // Prefer data over instructions end FAULT: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; - assign MMUTranslationComplete = '1; - assign InstrPageFaultM = ~DTLBMissM; - assign LoadPageFaultM = DTLBMissM && ~MemStore; - assign StorePageFaultM = DTLBMissM && MemStore; + TranslationPAdr = {CurrentPPN, VPN0, 2'b00}; + MMUTranslationComplete = '1; + InstrPageFaultM = ~DTLBMissM; + LoadPageFaultM = DTLBMissM && ~MemStore; + StorePageFaultM = DTLBMissM && MemStore; end endcase end @@ -232,11 +238,8 @@ module pagetablewalker ( logic GigapageMisaligned, BadGigapage; - typedef enum {IDLE, LEVEL2, LEVEL1, LEVEL0, LEAF, FAULT} walker_statetype; - walker_statetype WalkerState, NextWalkerState; - // *** Do we need a synchronizer here for walker to talk to ahblite? - flopenl #(.TYPE(walker_statetype)) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); + flopenl #(3) mmureg(HCLK, ~HRESETn, 1'b1, NextWalkerState, IDLE, WalkerState); always_comb begin case (WalkerState) @@ -279,42 +282,42 @@ module pagetablewalker ( // *** Should translate this flop block into our flop module notation always_comb begin // default values - assign TranslationPAdr = '0; - assign PageTableEntry = '0; - assign PageType = '0; - assign MMUTranslationComplete = '0; - assign DTLBWriteM = '0; - assign ITLBWriteF = '0; - assign InstrPageFaultM = '0; - assign LoadPageFaultM = '0; - assign StorePageFaultM = '0; + TranslationPAdr = '0; + PageTableEntry = '0; + PageType = '0; + MMUTranslationComplete = '0; + DTLBWriteM = '0; + ITLBWriteF = '0; + InstrPageFaultM = '0; + LoadPageFaultM = '0; + StorePageFaultM = '0; case (NextWalkerState) LEVEL2: begin - assign TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; + TranslationPAdr = {BasePageTablePPN, VPN2, 3'b000}; end LEVEL1: begin - assign TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; + TranslationPAdr = {CurrentPPN, VPN1, 3'b000}; end LEVEL0: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; end LEAF: begin // Keep physical address alive to prevent HADDR dropping to 0 - assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - assign PageTableEntry = CurrentPTE; - assign PageType = (WalkerState == LEVEL2) ? 2'b11 : + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + PageTableEntry = CurrentPTE; + PageType = (WalkerState == LEVEL2) ? 2'b11 : ((WalkerState == LEVEL1) ? 2'b01 : 2'b00); - assign MMUTranslationComplete = '1; - assign DTLBWriteM = DTLBMissM; - assign ITLBWriteF = ~DTLBMissM; // Prefer data over instructions + MMUTranslationComplete = '1; + DTLBWriteM = DTLBMissM; + ITLBWriteF = ~DTLBMissM; // Prefer data over instructions end FAULT: begin - assign TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; - assign MMUTranslationComplete = '1; - assign InstrPageFaultM = ~DTLBMissM; - assign LoadPageFaultM = DTLBMissM && ~MemStore; - assign StorePageFaultM = DTLBMissM && MemStore; + TranslationPAdr = {CurrentPPN, VPN0, 3'b000}; + MMUTranslationComplete = '1; + InstrPageFaultM = ~DTLBMissM; + LoadPageFaultM = DTLBMissM && ~MemStore; + StorePageFaultM = DTLBMissM && MemStore; end endcase end @@ -331,4 +334,4 @@ module pagetablewalker ( end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index 9d58fd0f..91073c0e 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -22,6 +22,7 @@ module fpu ( //signals, modules, and combinational logic closely defined. //used for OSU DP-size hardware to wally XLEN interfacing + integer XLENDIFF; assign XLENDIFF = `XLEN - 64; integer XLENDIFFN; @@ -465,13 +466,18 @@ module fpu ( always_comb begin //zero extension - if(`XLEN > 64) begin - FPUResultW <= {FPUResultDirW,{XLENDIFF{1'b0}}}; - end + +// Teo 04/13/2021 +// Commented out XLENDIFF{1'b0} due to error: +// Repetition multiplier must be constant. + + //if(`XLEN > 64) begin + // FPUResultW <= {FPUResultDirW,{XLENDIFF{1'b0}}}; + //end //truncate - else begin + //else begin FPUResultW <= FPUResultDirW[63:64-`XLEN]; - end + //end end diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index 4208c355..10f52b59 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -94,9 +94,9 @@ module icache( // Read from memory if we don't have the address we want always_comb if (LastReadDataValidF & (InstrPAdrF == LastReadAdrF)) begin - assign InstrReadF = 0; + InstrReadF = 0; end else begin - assign InstrReadF = 1; + InstrReadF = 1; end // Pick from the memory input or from the previous read, as appropriate @@ -128,11 +128,11 @@ module icache( // incomplete, since the pipeline stalls for us when it isn't), or a NOP for // the cycle when the first of two reads comes in. always_comb if (~FlushDLastCyclen) begin - assign InstrDMuxChoice = 2'b10; + InstrDMuxChoice = 2'b10; end else if (DelayD & (MisalignedHalfInstrD[1:0] != 2'b11)) begin - assign InstrDMuxChoice = 2'b11; + InstrDMuxChoice = 2'b11; end else begin - assign InstrDMuxChoice = {1'b0, DelayD}; + InstrDMuxChoice = {1'b0, DelayD}; end mux4 #(32) instrDMux (AlignedInstrD, {InstrInF[15:0], MisalignedHalfInstrD}, nop, {16'b0, MisalignedHalfInstrD}, InstrDMuxChoice, InstrRawD); endmodule diff --git a/wally-pipelined/src/mmu/cam_line.sv b/wally-pipelined/src/mmu/cam_line.sv index 36765b27..e74ac53b 100644 --- a/wally-pipelined/src/mmu/cam_line.sv +++ b/wally-pipelined/src/mmu/cam_line.sv @@ -24,9 +24,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" -`include "wally-constants.vh" - module cam_line #(parameter KEY_BITS = 20, parameter HIGH_SEGMENT_BITS = 10) ( input clk, reset, @@ -76,4 +73,4 @@ module cam_line #(parameter KEY_BITS = 20, assign Match = ({1'b1, VirtualPageNumberQuery} == Key); -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 066e0c42..9aae039e 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -24,9 +24,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" -`include "wally-constants.vh" - /** * sv32 specs * ---------- @@ -52,6 +49,9 @@ * least recently) */ +`include "wally-config.vh" +`include "wally-constants.vh" + // The TLB will have 2**ENTRY_BITS total entries module tlb #(parameter ENTRY_BITS = 3) ( input clk, reset, diff --git a/wally-pipelined/src/mmu/tlb_ram.sv b/wally-pipelined/src/mmu/tlb_ram.sv index 059a9aa5..7e24a0a2 100644 --- a/wally-pipelined/src/mmu/tlb_ram.sv +++ b/wally-pipelined/src/mmu/tlb_ram.sv @@ -57,4 +57,4 @@ module tlb_ram #(parameter ENTRY_BITS = 3) ( ram[i] = `XLEN'b0; end -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/mmu/tlb_rand.sv b/wally-pipelined/src/mmu/tlb_rand.sv index 68a5acad..afb0bb2c 100644 --- a/wally-pipelined/src/mmu/tlb_rand.sv +++ b/wally-pipelined/src/mmu/tlb_rand.sv @@ -29,7 +29,7 @@ module tlb_rand #(parameter ENTRY_BITS = 3) ( ); logic [31:0] data; - assign data = $urandom; + assign data = 32'b0; assign WriteIndex = data[ENTRY_BITS-1:0]; endmodule diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index 38bdf0f0..78aea323 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -1479,21 +1479,15 @@ module shifter_l64 (Z, A, Shift); logic [63:0] stage3; logic [63:0] stage4; logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [63:0] Z; - mux2 #(64) mx01(A, {A[31:0], thirtytwozeros}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {stage1[47:0], sixteenzeros}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {stage2[55:0], eightzeros}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {stage3[59:0], fourzeros}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {stage4[61:0], twozeros}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {stage5[62:0], onezero}, Shift[0], Z); + mux2 #(64) mx01(A, {A[31:0], 32'h0}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {stage1[47:0], 16'h0}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {stage2[55:0], 8'h0}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {stage3[59:0], 4'h0}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {stage4[61:0], 2'h0}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {stage5[62:0], 1'h0}, Shift[0], Z); endmodule // shifter_l64 @@ -1507,21 +1501,15 @@ module shifter_r64 (Z, A, Shift); logic [63:0] stage3; logic [63:0] stage4; logic [63:0] stage5; - logic [31:0] thirtytwozeros = 32'h0; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [63:0] Z; - mux2 #(64) mx01(A, {thirtytwozeros, A[63:32]}, Shift[5], stage1); - mux2 #(64) mx02(stage1, {sixteenzeros, stage1[63:16]}, Shift[4], stage2); - mux2 #(64) mx03(stage2, {eightzeros, stage2[63:8]}, Shift[3], stage3); - mux2 #(64) mx04(stage3, {fourzeros, stage3[63:4]}, Shift[2], stage4); - mux2 #(64) mx05(stage4, {twozeros, stage4[63:2]}, Shift[1], stage5); - mux2 #(64) mx06(stage5, {onezero, stage5[63:1]}, Shift[0], Z); + mux2 #(64) mx01(A, {32'h0, A[63:32]}, Shift[5], stage1); + mux2 #(64) mx02(stage1, {16'h0, stage1[63:16]}, Shift[4], stage2); + mux2 #(64) mx03(stage2, {8'h0, stage2[63:8]}, Shift[3], stage3); + mux2 #(64) mx04(stage3, {4'h0, stage3[63:4]}, Shift[2], stage4); + mux2 #(64) mx05(stage4, {2'h0, stage4[63:2]}, Shift[1], stage5); + mux2 #(64) mx06(stage5, {1'h0, stage5[63:1]}, Shift[0], Z); endmodule // shifter_r64 @@ -1534,19 +1522,14 @@ module shifter_l32 (Z, A, Shift); logic [31:0] stage2; logic [31:0] stage3; logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [31:0] Z; - mux2 #(32) mx01(A, {A[15:0], sixteenzeros}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {stage1[23:0], eightzeros}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {stage2[27:0], fourzeros}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {stage3[29:0], twozeros}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {stage4[30:0], onezero}, Shift[0], Z); + mux2 #(32) mx01(A, {A[15:0], 16'h0}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {stage1[23:0], 8'h0}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {stage2[27:0], 4'h0}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {stage3[29:0], 2'h0}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {stage4[30:0], 1'h0}, Shift[0], Z); endmodule // shifter_l32 @@ -1559,19 +1542,14 @@ module shifter_r32 (Z, A, Shift); logic [31:0] stage2; logic [31:0] stage3; logic [31:0] stage4; - logic [15:0] sixteenzeros = 16'h0; - logic [ 7:0] eightzeros = 8'h0; - logic [ 3:0] fourzeros = 4'h0; - logic [ 1:0] twozeros = 2'b00; - logic onezero = 1'b0; output logic [31:0] Z; - mux2 #(32) mx01(A, {sixteenzeros, A[31:16]}, Shift[4], stage1); - mux2 #(32) mx02(stage1, {eightzeros, stage1[31:8]}, Shift[3], stage2); - mux2 #(32) mx03(stage2, {fourzeros, stage2[31:4]}, Shift[2], stage3); - mux2 #(32) mx04(stage3, {twozeros, stage3[31:2]}, Shift[1], stage4); - mux2 #(32) mx05(stage4, {onezero, stage4[31:1]}, Shift[0], Z); + mux2 #(32) mx01(A, {16'h0, A[31:16]}, Shift[4], stage1); + mux2 #(32) mx02(stage1, {8'h0, stage1[31:8]}, Shift[3], stage2); + mux2 #(32) mx03(stage2, {4'h0, stage2[31:4]}, Shift[2], stage3); + mux2 #(32) mx04(stage3, {2'h0, stage3[31:2]}, Shift[1], stage4); + mux2 #(32) mx05(stage4, {1'h0, stage4[31:1]}, Shift[0], Z); endmodule // shifter_r32 diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index dbf21e91..07ca9fb3 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -80,7 +80,7 @@ module csrc ( for (j=0; j<= `COUNTERS; j = j+1) begin // Write enables - if (j !==1) begin + if (j != 1) begin assign WriteHPMCOUNTERM[j] = CSRMWriteM && (CSRAdrM == MHPMCOUNTER[j]); // Count Signals assign HPMCOUNTERPlusM[j] = HPMCOUNTER_REGW[j] + {63'b0, MCOUNTEN[j] & ~MCOUNTINHIBIT_REGW[j]}; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 9b2bfe6a..18ef2a50 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -24,6 +24,7 @@ /////////////////////////////////////////// `include "wally-config.vh" +`include "wally-constants.vh" /* verilator lint_on UNUSED */ module wallypipelinedhart (