From 08a7f6ec254f0bc3e1d67eee2164b11fbf112969 Mon Sep 17 00:00:00 2001
From: Teo Ene <teodor@rivendell.ecen.okstate.edu>
Date: Thu, 4 Mar 2021 01:27:05 -0600
Subject: [PATCH] In the process of updating coremark.RV64I program to work
 with Dr. Harris's perl script. Commiting to make it easier to switch branches

---
 wally-pipelined/config/coremark/wally-config.vh |  7 +++----
 wally-pipelined/regression/wally-coremark.do    | 14 +++++++++-----
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh
index 906373f9..de4d0366 100644
--- a/wally-pipelined/config/coremark/wally-config.vh
+++ b/wally-pipelined/config/coremark/wally-config.vh
@@ -56,8 +56,7 @@
 `define MEM_VIRTMEM 0
 
 // Address space
-//`define RESET_VECTOR 64'h0000000080000000
-`define RESET_VECTOR 64'h0000000000000000
+`define RESET_VECTOR 64'h0000000080000000
 
 // Bus Interface width
 `define AHBW 64
@@ -66,8 +65,8 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define TIMBASE    32'h00000000
-`define TIMRANGE   32'h0007FFFF
+`define TIMBASE    32'h80000000
+`define TIMRANGE   32'h00007FFF
 `define CLINTBASE  32'h02000000
 `define CLINTRANGE 32'h0000FFFF
 `define GPIOBASE   32'h10012000
diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do
index f3205ae5..2627a596 100644
--- a/wally-pipelined/regression/wally-coremark.do
+++ b/wally-pipelined/regression/wally-coremark.do
@@ -76,7 +76,7 @@ add wave /testbench/InstrWName
 #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
 #add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
 #add wave /testbench/dut/hart/ieu/dp/PCSrcE
-add wave -divider Regfile
+add wave -divider Regfile_signals
 #add wave /testbench/dut/uncore/dtim/memwrite
 #add wave -hex /testbench/dut/uncore/HADDR
 #add wave -hex /testbench/dut/uncore/HWDATA
@@ -86,11 +86,14 @@ add wave -divider Regfile
 #add wave /testbench/dut/hart/ieu/dp/RegWriteW
 #add wave -hex /testbench/dut/hart/ieu/dp/ResultW
 #add wave -hex /testbench/dut/hart/ieu/dp/RdW
-#add wave -hex -r /testbench/*
 add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
+add wave -divider Regfile_itself
+add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
+add wave -divider RAM
+add wave -hex -r /testbench/dut/uncore/dtim/RAM
 add wave -divider Misc
 add wave -divider
-#add wave -hex -r /testbench/dut/uncore/dtim/RAM
+add wave -hex -r /testbench/*
 
 -- Set Wave Output Items 
 TreeUpdate [SetDefaultTree]
@@ -106,6 +109,7 @@ configure wave -childrowmargin 2
 set DefaultRadix hexadecimal
 
 -- Run the Simulation 
-#run 3000
-run -all
+#run 7402000
+run 2780
+#run -all
 #quit