diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh
index 5c210ebd..6f97c5f3 100644
--- a/pipelined/config/shared/wally-shared.vh
+++ b/pipelined/config/shared/wally-shared.vh
@@ -108,6 +108,7 @@
 `define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ))
 `define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+6) ? (`DIVRESLEN+`NF) : (3*`NF+4))
 
+/*
 // division constants
 `define RADIX 32'h4
 `define DIVCOPIES 32'h4
@@ -129,6 +130,22 @@
 `define DIVb (`QLEN-1)
 `define DIVa (`DIVb+1-`XLEN)
 `define DIVBLEN ($clog2(`DIVb+1)-1)
+*/
+
+// division constants
+`define RADIX       32'h4
+`define DIVCOPIES   32'h4
+`define DIVN        (`NF<`XLEN ? `XLEN : `NF+3) // standard length of input
+`define DIVRESLEN   (`NF<`XLEN ? `XLEN : `NF+4) // result length for postprocessing
+`define LOGR        (`RADIX==2 ? 32'h1 : 32'h2) // r = log(R)
+`define RK          (`LOGR*`DIVCOPIES)          // r*k used for intdiv preproc
+`define LOGRK       ($clog2(`RK))               // log2(r*k)
+`define FPDUR       ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4))
+`define DURLEN      ($clog2(`FPDUR+1))
+`define QLEN        (`FPDUR*`LOGR*`DIVCOPIES)
+`define DIVb        (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size
+`define DIVBLEN     ($clog2(`DIVb+1)-1)
+`define DIVa        (`DIVb+1-`XLEN)             // used for idiv on fpu
 
 
 `define USE_SRAM 0
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
index 919f7b05..e9ec6618 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -71,7 +71,7 @@ module fdivsqrtiter(
  
   // Residual WS/SC registers/initializaiton mux
   mux2   #(`DIVb+4) wsmux(WS[`DIVCOPIES], X, IFDivStartE, WSN);
-  mux2   #(`DIVb+4) wcmux(WC[`DIVCOPIES], 0, IFDivStartE, WCN);
+  mux2   #(`DIVb+4) wcmux(WC[`DIVCOPIES], '0, IFDivStartE, WCN);
   flopen #(`DIVb+4) wsreg(clk, FDivBusyE, WSN, WS[0]);
   flopen #(`DIVb+4) wcreg(clk, FDivBusyE, WCN, WC[0]);
 
@@ -88,10 +88,11 @@ module fdivsqrtiter(
   // Initialize C to -1 for sqrt and -R for division
   logic [1:0] initCUpper;
   if(`RADIX == 4) begin
-    mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, InitCUpper);
+    mux2 #(2) cuppermux4(2'b00, 2'b11, SqrtE, initCUpper);
   end else begin
-    mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, InitCUpper);
+    mux2 #(2) cuppermux2(2'b10, 2'b11, SqrtE, initCUpper);
   end
+  
   assign initC = {initCUpper, {`DIVb{1'b0}}};
   mux2   #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); 
   flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]);