From 0670c57fd2638defa89c97712dfaedaed5ddf3c9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Tue, 1 Jun 2021 15:05:22 -0500
Subject: [PATCH] The clock gater was not implemented correctly.  Now it is
 level sensitive to a low clock.

---
 wally-pipelined/src/generic/clockgater.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/src/generic/clockgater.sv b/wally-pipelined/src/generic/clockgater.sv
index dc51829d..c06a1cbd 100644
--- a/wally-pipelined/src/generic/clockgater.sv
+++ b/wally-pipelined/src/generic/clockgater.sv
@@ -38,7 +38,7 @@ module clockgater
   logic 	enable_q;
   
 
-  always @(E or SE) begin
+  always @(~CLK) begin
     enable_q <= E | SE;
   end
   assign ECLK = enable_q & CLK;