diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
index 92f64cbd..e8708c6c 100644
--- a/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -57,7 +57,7 @@ module fdivsqrt(
 
   logic [`DIVb+3:0]           WS, WC;                       // Partial remainder components
   logic [`DIVb+3:0]           X;                            // Iterator Initial Value (from dividend)
-  logic [`DIVb-1:0]           DPreproc, D;                  // Iterator Divisor
+  logic [`DIVb-1:0]           D;                  // Iterator Divisor
   logic [`DIVb:0]             FirstU, FirstUM;              // Intermediate result values
   logic [`DIVb+1:0]           FirstC;                       // Step tracker
   logic                       Firstun;                      // Quotient selection
@@ -75,8 +75,7 @@ module fdivsqrt(
 
   fdivsqrtpreproc fdivsqrtpreproc(                        // Preprocessor
     .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), 
-    .Fmt(FmtE), .Sqrt(SqrtE), .XZeroE, .Funct3E, 
-    .QeM, .X, .DPreproc, 
+    .Fmt(FmtE), .Sqrt(SqrtE), .XZeroE, .Funct3E, .QeM, .X, .D, 
     // Int-specific 
     .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
     .nE, .BZeroM, .nM, .mM, .AM, 
@@ -90,8 +89,8 @@ module fdivsqrt(
     .IDivStartE, .ISpecialCaseE, .nE, .IntDivE);
 
   fdivsqrtiter fdivsqrtiter(                              // CSA Iterator
-    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .DPreproc, 
-    .D, .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
+    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, 
+    .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
 
   fdivsqrtpostproc fdivsqrtpostproc(                      // Postprocessor
     .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
index ec15423e..f3048c8b 100644
--- a/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -34,8 +34,7 @@ module fdivsqrtiter(
   input  logic             FDivBusyE, 
   input  logic             SqrtE,
   input  logic [`DIVb+3:0] X,
-  input  logic [`DIVb-1:0] DPreproc,
-  output logic [`DIVb-1:0] D,
+  input  logic [`DIVb-1:0] D,
   output logic [`DIVb:0]   FirstU, FirstUM,
   output logic [`DIVb+1:0] FirstC,
   output logic             Firstun,
@@ -95,9 +94,6 @@ module fdivsqrtiter(
   mux2   #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); 
   flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
 
-   // Divisior register
-  flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);
-
   // Divisor Selections
   //  - choose the negitive version of what's being selected
   //  - D is a 0.b mantissa
diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index cf8a055e..4af1d786 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -39,7 +39,7 @@ module fdivsqrtpreproc (
   input  logic [2:0]          Funct3E,
   output logic [`NE+1:0]      QeM,
   output logic [`DIVb+3:0]    X,
-  output logic [`DIVb-1:0]    DPreproc,
+  output logic [`DIVb-1:0]    D,
   // Int-specific
   input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   input  logic                IntDivE, W64E,
@@ -50,7 +50,7 @@ module fdivsqrtpreproc (
   output logic [`XLEN-1:0]    AM
 );
 
-  logic [`DIVb-1:0]           XPreproc;
+  logic [`DIVb-1:0]           XPreproc, DPreproc;
   logic [`DIVb:0]             PreSqrtX;
   logic [`DIVb+3:0]           DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
   logic [`NE+1:0]             QeE;                                 // Quotient Exponent (FP only)
@@ -173,5 +173,8 @@ module fdivsqrtpreproc (
   // Floating-point exponent
   fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
   flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
+
+   // Divisior register
+  flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);
 endmodule