From 0502b8ea4d8cb489f3bf7b0723cfa12ec16af6d9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Nov 2022 04:17:37 -0800 Subject: [PATCH] Comments about division hazards --- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 1 + pipelined/src/hazard/hazard.sv | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8dc188c6..c64dbc87 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -118,6 +118,7 @@ module fdivsqrtfsm( end end + // *** start logic is presently in fctl. Make it look more like integer division start logic assign DivDone = (state == DONE) | (WZero & (state == BUSY)); assign DivBusy = (state == BUSY & ~DivDone); diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0ca3c5bc..4eba6700 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -70,7 +70,7 @@ module hazard( // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE? - assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); + assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); // *** FDivBusyE should look like DivBusyE in execute stage assign #1 StallF = StallFCause | StallD; assign #1 StallD = StallDCause | StallE;