From 6e78b46761b1f633114a389336a0529e9ed2a8b6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Aug 2022 16:13:16 -0700 Subject: [PATCH 1/2] Completed LZA simplificaiton --- pipelined/src/fpu/fma.sv | 4 ++-- pipelined/src/fpu/fmaadd.sv | 12 ++++++------ pipelined/src/fpu/fmalza.sv | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index dec492eb..950b55ff 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -51,7 +51,7 @@ module fma( logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format logic [3*`NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+5.2NF+1) - logic [3*`NF+6:0] AmInv; // aligned addend's mantissa possibly inverted + logic [3*`NF+5:0] AmInv; // aligned addend's mantissa possibly inverted logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed /////////////////////////////////////////////////////////////////////////////// // Calculate the product @@ -86,7 +86,7 @@ module fma( fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss); - fmalza lza(.A(AmInv[3*`NF+5:0]), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); + fmalza lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); endmodule diff --git a/pipelined/src/fpu/fmaadd.sv b/pipelined/src/fpu/fmaadd.sv index 4b52208c..56ce5a74 100644 --- a/pipelined/src/fpu/fmaadd.sv +++ b/pipelined/src/fpu/fmaadd.sv @@ -37,7 +37,7 @@ module fmaadd( input logic ZmSticky, input logic [`NE-1:0] Ze, input logic [`NE+1:0] Pe, - output logic [3*`NF+6:0] AmInv, // aligned addend possibly inverted + output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed output logic NegSum, // was the sum negitive output logic InvA, // do you invert the aligned addend @@ -45,7 +45,7 @@ module fmaadd( output logic [`NE+1:0] Se, output logic [3*`NF+5:0] Sm // the positive sum ); - logic [3*`NF+6:0] PreSum, NegPreSum; // possibly negitive sum + logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum /////////////////////////////////////////////////////////////////////////////// // Addition @@ -57,7 +57,7 @@ module fmaadd( assign InvA = As ^ Ps; // Choose an inverted or non-inverted addend - the one has to be added now for the LZA - assign AmInv = InvA ? {1'b1, ~Am} : {1'b0, Am}; + assign AmInv = InvA ? ~Am : Am; // Kill the product if the product is too small to effect the addition (determined in fma1.sv) assign PmKilled = Pm&{2*`NF+2{~KillProd}}; // Do the addition @@ -66,11 +66,11 @@ module fmaadd( // PreSum -1 = don't add 1 +1 = add 2 // NegPreSum +1 = add 2 -1 = don't add 1 // for NegPreSum the product is set to -1 whenever the product is killed, therefore add 1, 2 or 0 - assign PreSum = {{`NF+3{1'b0}}, PmKilled, 1'b0, InvA&ZmSticky&KillProd} + AmInv + {{3*`NF+6{1'b0}}, InvA&~((ZmSticky&~KillProd))}; - assign NegPreSum = {1'b0, Am} + {{`NF+3{1'b1}}, ~PmKilled, 2'b11} + {(3*`NF+5)'(0), ZmSticky&~KillProd, ~(ZmSticky)}; + assign PreSum = {{`NF+2{1'b0}}, PmKilled, 1'b0, InvA&ZmSticky&KillProd} + AmInv + {{3*`NF+5{1'b0}}, InvA&~((ZmSticky&~KillProd))}; + assign NegPreSum = Am + {{`NF+2{1'b1}}, ~PmKilled, 2'b11} + {(3*`NF+4)'(0), ZmSticky&~KillProd, ~(ZmSticky)}; // Is the sum negitive - assign NegSum = PreSum[3*`NF+6]; + assign NegSum = PreSum[3*`NF+5]; // Choose the positive sum and accompanying LZA result. assign Sm = NegSum ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0]; diff --git a/pipelined/src/fpu/fmalza.sv b/pipelined/src/fpu/fmalza.sv index fd180fbb..65fe9426 100644 --- a/pipelined/src/fpu/fmalza.sv +++ b/pipelined/src/fpu/fmalza.sv @@ -39,7 +39,7 @@ module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, localparam WIDTH = 3*`NF+6; - logic [WIDTH:0] F; + logic [WIDTH:0] F; logic [WIDTH-1:0] B, P, G, K; logic [WIDTH-1:0] Pp1, Gm1, Km1; From 8b44037f58a13b1e37ee7729d01bd6a78712c9b5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Aug 2022 16:18:02 -0700 Subject: [PATCH 2/2] Parameterized fmalza --- pipelined/src/fpu/fma.sv | 4 ++-- pipelined/src/fpu/fmalza.sv | 8 +++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 950b55ff..0106af7d 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -85,8 +85,8 @@ module fma( fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss); - - fmalza lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); + + fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); endmodule diff --git a/pipelined/src/fpu/fmalza.sv b/pipelined/src/fpu/fmalza.sv index 65fe9426..8e92a5dc 100644 --- a/pipelined/src/fpu/fmalza.sv +++ b/pipelined/src/fpu/fmalza.sv @@ -29,16 +29,14 @@ `include "wally-config.vh" -module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] - input logic [3*`NF+5:0] A, // addend +module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] + input logic [WIDTH-1:0] A, // addend input logic [2*`NF+3:0] Pm, // product input logic Cin, // carry in input logic sub, - output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count for the positive result + output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result ); - localparam WIDTH = 3*`NF+6; - logic [WIDTH:0] F; logic [WIDTH-1:0] B, P, G, K; logic [WIDTH-1:0] Pp1, Gm1, Km1;