From 03021765a6781ca2d16cbcc7256238ac6e62b462 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 22 Dec 2022 21:43:25 -0600 Subject: [PATCH] The LSU is properly using FlushW rather than TrapM. --- pipelined/src/hazard/hazard.sv | 2 +- pipelined/src/wally/wallypipelinedcore.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 7191fb61..c14162e6 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -87,7 +87,7 @@ module hazard( // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //assign StallWCause = (IFUStallF | LSUStallM) & ~TrapM; - assign StallWCause = (IFUStallF & ~(FlushDCause)) | (LSUStallM & ~TrapM); + assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause); // Stall each stage for cause or if the next stage is stalled assign #1 StallF = StallFCause | StallD; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index f33d0f4a..46f6520d 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -247,7 +247,7 @@ module wallypipelinedcore ( lsu lsu( .clk, .reset, .StallM, .FlushM, .StallW, - .FlushW(TrapM), + .FlushW, // CPU interface .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,