From 02e924e55a0fb2d9af25cae78b8b62a0637b77e9 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Thu, 25 Mar 2021 00:16:26 -0400
Subject: [PATCH] instrfaults not respecting stalls bugfix

---
 wally-pipelined/src/ifu/ifu.sv               | 2 +-
 wally-pipelined/src/privileged/privileged.sv | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index bad52a94..eb65e167 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -162,7 +162,7 @@ module ifu (
   endgenerate
 
   // Decode stage pipeline register and logic
-  flopenl #(32)    InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD);
+  flopenl #(32)    InstrDReg(clk, reset, ~StallD | FlushD, (FlushD ? nop : InstrF), nop, InstrRawD);
   flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 8a6854e9..c967d262 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -125,10 +125,10 @@ module privileged (
 
   // pipeline fault signals
   flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD);
-  floprc #(2) faultregE(clk, reset, FlushE,
+  flopenrc #(2) faultregE(clk, reset, FlushE, ~StallE,
                            {IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD
                            {IllegalIEUInstrFaultE, InstrAccessFaultE});
-  floprc #(2) faultregM(clk, reset, FlushM,
+  flopenrc #(2) faultregM(clk, reset, FlushM, ~StallM,
                          {IllegalIEUInstrFaultE, InstrAccessFaultE},
                          {IllegalIEUInstrFaultM, InstrAccessFaultM});