diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile
index 6174464e..f1501328 100644
--- a/pipelined/regression/Makefile
+++ b/pipelined/regression/Makefile
@@ -24,8 +24,10 @@ clean:
 
 riscoftests: 
 # 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
-	make -C ../../tests/riscof/
-	make -C ../../tests/riscof/ XLEN=32
+	make -C ../../tests/riscof/ 
+#	make -C ../../tests/riscof/ XLEN=32
+#	make -C ../../tests/riscof/ XLEN=32 build_rv32e
+#	make -C ../../tests/riscof/ XLEN=64
 
 memfiles:
 	make -f makefile-memfile wally-sim-files --jobs
diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index 821246a5..c86f1953 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -64,7 +64,7 @@ tc = TestCase(
       grepstr="400100000 instructions")
 configs.append(tc)
 
-tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64periph", "wally64priv"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
+tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64f", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64periph", "wally64priv"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
   tc = TestCase(
         name=test,
@@ -73,7 +73,7 @@ for test in tests64gc:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
-tests32gc = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32f", "imperas32m", "wally32a",  "imperas32c", "wally32priv", "wally32periph"]  #, "imperas32mmu""wally32i", 
+tests32gc = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "arch32d", "imperas32i", "imperas32f", "imperas32m", "wally32a",  "imperas32c", "wally32priv", "wally32periph"]  #, "imperas32mmu""wally32i", 
 for test in tests32gc:
   tc = TestCase(
         name=test,
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv
index dcb04883..a55350c6 100644
--- a/pipelined/src/uncore/uartPC16550D.sv
+++ b/pipelined/src/uncore/uartPC16550D.sv
@@ -328,9 +328,9 @@ module uartPC16550D(
         rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0;
       end else if (rxstate == UART_DONE) begin
         RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
-        if (rxoverrunerr) $warning("UART RX Overrun Error\n");
-        if (rxparityerr) $warning("UART RX Parity Error\n");
-        if (rxframingerr) $warning("UART RX Framing Error\n");
+        if (rxoverrunerr) $warning("UART RX Overrun Err\n");
+        if (rxparityerr) $warning("UART RX Parity Err\n");
+        if (rxframingerr) $warning("UART RX Framing Err\n");
         if (fifoenabled) begin
           rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
           rxfifohead <= #1 rxfifohead + 1;
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 9bc1ce24..3aa123fc 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -89,7 +89,8 @@ logic [3:0] dummy;
                           if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
                           else                  tests = {arch64c};
         "arch64m":      if (`M_SUPPORTED) tests = arch64m;
-        "arch64d":      if (`D_SUPPORTED) tests = arch64d;
+        "arch64f":      if (`F_SUPPORTED) tests = arch64f;
+        "arch64d":      if (`D_SUPPORTED) tests = arch64d;  
         "imperas64i":                     tests = imperas64i;
         "imperas64f":   if (`F_SUPPORTED) tests = imperas64f;
         "imperas64d":   if (`D_SUPPORTED) tests = imperas64d;
@@ -112,9 +113,9 @@ logic [3:0] dummy;
                           else                  tests = {arch32c};
         "arch32m":      if (`M_SUPPORTED) tests = arch32m;
         "arch32f":      if (`F_SUPPORTED) tests = arch32f;
+        "arch32d":      if (`D_SUPPORTED) tests = arch32d;
         "imperas32i":                     tests = imperas32i;
         "imperas32f":   if (`F_SUPPORTED) tests = imperas32f;
-        // "wally32d":     if (`D_SUPPORTED) tests = wally32d;
         "imperas32m":   if (`M_SUPPORTED) tests = imperas32m;
         "wally32a":     if (`A_SUPPORTED) tests = wally32a;
         "imperas32c":   if (`C_SUPPORTED) tests = imperas32c;
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index 9d4f7854..587733c3 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -1052,6 +1052,157 @@ string imperas32f[] = '{
     "rv64i_m/I/src/xori-01.S"
   };
 
+  string arch64f[] = '{
+    `RISCVARCHTEST,
+    "rv64i_m/F/src/fadd_b10-01.S",
+    "rv64i_m/F/src/fadd_b1-01.S",
+    "rv64i_m/F/src/fadd_b11-01.S",
+    "rv64i_m/F/src/fadd_b12-01.S",
+    "rv64i_m/F/src/fadd_b13-01.S",
+    "rv64i_m/F/src/fadd_b2-01.S",
+    "rv64i_m/F/src/fadd_b3-01.S",
+    "rv64i_m/F/src/fadd_b4-01.S",
+    "rv64i_m/F/src/fadd_b5-01.S",
+    "rv64i_m/F/src/fadd_b7-01.S",
+    "rv64i_m/F/src/fadd_b8-01.S",
+    "rv64i_m/F/src/fclass_b1-01.S",
+    "rv64i_m/F/src/fcvt.s.w_b25-01.S",
+    "rv64i_m/F/src/fcvt.s.w_b26-01.S",
+    "rv64i_m/F/src/fcvt.s.wu_b25-01.S",
+    "rv64i_m/F/src/fcvt.s.wu_b26-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b1-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b22-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b23-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b24-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b27-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b28-01.S",
+    "rv64i_m/F/src/fcvt.w.s_b29-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b1-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b22-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b23-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b24-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b27-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b28-01.S",
+    "rv64i_m/F/src/fcvt.wu.s_b29-01.S",
+    "rv64i_m/F/src/fdiv_b1-01.S",
+    "rv64i_m/F/src/fdiv_b20-01.S",
+    "rv64i_m/F/src/fdiv_b2-01.S",
+    "rv64i_m/F/src/fdiv_b21-01.S",
+    "rv64i_m/F/src/fdiv_b3-01.S",
+    "rv64i_m/F/src/fdiv_b4-01.S",
+    "rv64i_m/F/src/fdiv_b5-01.S",
+    "rv64i_m/F/src/fdiv_b6-01.S",
+    "rv64i_m/F/src/fdiv_b7-01.S",
+    "rv64i_m/F/src/fdiv_b8-01.S",
+    "rv64i_m/F/src/fdiv_b9-01.S",
+    "rv64i_m/F/src/feq_b1-01.S",
+    "rv64i_m/F/src/feq_b19-01.S",
+    "rv64i_m/F/src/fle_b1-01.S",
+    "rv64i_m/F/src/fle_b19-01.S",
+    "rv64i_m/F/src/flt_b1-01.S",
+    "rv64i_m/F/src/flt_b19-01.S",
+    // "rv64i_m/F/src/flw-align-01.S",
+    "rv64i_m/F/src/fmadd_b1-01.S",
+    "rv64i_m/F/src/fmadd_b14-01.S",
+    // "rv64i_m/F/src/fmadd_b15-01.S",
+    "rv64i_m/F/src/fmadd_b16-01.S",
+    "rv64i_m/F/src/fmadd_b17-01.S",
+    "rv64i_m/F/src/fmadd_b18-01.S",
+    "rv64i_m/F/src/fmadd_b2-01.S",
+    "rv64i_m/F/src/fmadd_b3-01.S",
+    "rv64i_m/F/src/fmadd_b4-01.S",
+    "rv64i_m/F/src/fmadd_b5-01.S",
+    "rv64i_m/F/src/fmadd_b6-01.S",
+    "rv64i_m/F/src/fmadd_b7-01.S",
+    "rv64i_m/F/src/fmadd_b8-01.S",
+    "rv64i_m/F/src/fmax_b1-01.S",
+    "rv64i_m/F/src/fmax_b19-01.S",
+    "rv64i_m/F/src/fmin_b1-01.S",
+    "rv64i_m/F/src/fmin_b19-01.S",
+    "rv64i_m/F/src/fmsub_b1-01.S",
+    "rv64i_m/F/src/fmsub_b14-01.S",
+    "rv64i_m/F/src/fmsub_b15-01.S",
+    "rv64i_m/F/src/fmsub_b16-01.S",
+    "rv64i_m/F/src/fmsub_b17-01.S",
+    "rv64i_m/F/src/fmsub_b18-01.S",
+    "rv64i_m/F/src/fmsub_b2-01.S",
+    "rv64i_m/F/src/fmsub_b3-01.S",
+    "rv64i_m/F/src/fmsub_b4-01.S",
+    "rv64i_m/F/src/fmsub_b5-01.S",
+    "rv64i_m/F/src/fmsub_b6-01.S",
+    "rv64i_m/F/src/fmsub_b7-01.S",
+    "rv64i_m/F/src/fmsub_b8-01.S",
+    "rv64i_m/F/src/fmul_b1-01.S",
+    "rv64i_m/F/src/fmul_b2-01.S",
+    "rv64i_m/F/src/fmul_b3-01.S",
+    "rv64i_m/F/src/fmul_b4-01.S",
+    "rv64i_m/F/src/fmul_b5-01.S",
+    "rv64i_m/F/src/fmul_b6-01.S",
+    "rv64i_m/F/src/fmul_b7-01.S",
+    "rv64i_m/F/src/fmul_b8-01.S",
+    "rv64i_m/F/src/fmul_b9-01.S",
+    "rv64i_m/F/src/fmv.w.x_b25-01.S",
+    "rv64i_m/F/src/fmv.w.x_b26-01.S",
+    "rv64i_m/F/src/fmv.x.w_b1-01.S",
+    "rv64i_m/F/src/fmv.x.w_b22-01.S",
+    "rv64i_m/F/src/fmv.x.w_b23-01.S",
+    "rv64i_m/F/src/fmv.x.w_b24-01.S",
+    "rv64i_m/F/src/fmv.x.w_b27-01.S",
+    "rv64i_m/F/src/fmv.x.w_b28-01.S",
+    "rv64i_m/F/src/fmv.x.w_b29-01.S",
+    "rv64i_m/F/src/fnmadd_b1-01.S",
+    "rv64i_m/F/src/fnmadd_b14-01.S",
+    // "rv64i_m/F/src/fnmadd_b15-01.S",
+    "rv64i_m/F/src/fnmadd_b16-01.S",
+    "rv64i_m/F/src/fnmadd_b17-01.S",
+    "rv64i_m/F/src/fnmadd_b18-01.S",
+    "rv64i_m/F/src/fnmadd_b2-01.S",
+    "rv64i_m/F/src/fnmadd_b3-01.S",
+    "rv64i_m/F/src/fnmadd_b4-01.S",
+    "rv64i_m/F/src/fnmadd_b5-01.S",
+    "rv64i_m/F/src/fnmadd_b6-01.S",
+    "rv64i_m/F/src/fnmadd_b7-01.S",
+    "rv64i_m/F/src/fnmadd_b8-01.S",
+    "rv64i_m/F/src/fnmsub_b1-01.S",
+    "rv64i_m/F/src/fnmsub_b14-01.S",
+    // "rv64i_m/F/src/fnmsub_b15-01.S",
+    "rv64i_m/F/src/fnmsub_b16-01.S",
+    "rv64i_m/F/src/fnmsub_b17-01.S",
+    "rv64i_m/F/src/fnmsub_b18-01.S",
+    "rv64i_m/F/src/fnmsub_b2-01.S",
+    "rv64i_m/F/src/fnmsub_b3-01.S",
+    "rv64i_m/F/src/fnmsub_b4-01.S",
+    "rv64i_m/F/src/fnmsub_b5-01.S",
+    "rv64i_m/F/src/fnmsub_b6-01.S",
+    "rv64i_m/F/src/fnmsub_b7-01.S",
+    "rv64i_m/F/src/fnmsub_b8-01.S",
+    "rv64i_m/F/src/fsgnj_b1-01.S",
+    "rv64i_m/F/src/fsgnjn_b1-01.S",
+    "rv64i_m/F/src/fsgnjx_b1-01.S",
+    // "rv64i_m/F/src/fsqrt_b1-01.S",
+    // "rv64i_m/F/src/fsqrt_b20-01.S",
+    // "rv64i_m/F/src/fsqrt_b2-01.S",
+    // "rv64i_m/F/src/fsqrt_b3-01.S",
+    // "rv64i_m/F/src/fsqrt_b4-01.S",
+    // "rv64i_m/F/src/fsqrt_b5-01.S",
+    // "rv64i_m/F/src/fsqrt_b7-01.S",
+    // "rv64i_m/F/src/fsqrt_b8-01.S",
+    // "rv64i_m/F/src/fsqrt_b9-01.S",
+    "rv64i_m/F/src/fsub_b10-01.S",
+    "rv64i_m/F/src/fsub_b1-01.S",
+    "rv64i_m/F/src/fsub_b11-01.S",
+    "rv64i_m/F/src/fsub_b12-01.S",
+    "rv64i_m/F/src/fsub_b13-01.S",
+    "rv64i_m/F/src/fsub_b2-01.S",
+    "rv64i_m/F/src/fsub_b3-01.S",
+    "rv64i_m/F/src/fsub_b4-01.S",
+    "rv64i_m/F/src/fsub_b5-01.S",
+    "rv64i_m/F/src/fsub_b7-01.S",
+    "rv64i_m/F/src/fsub_b8-01.S"
+    // "rv64i_m/F/src/fsw-align-01.S"
+    };
+
+
   string arch64d[] = '{
     `RISCVARCHTEST,
     "rv64i_m/D/src/fadd.d_b10-01.S",
@@ -1408,6 +1559,153 @@ string imperas32f[] = '{
     // "rv32i_m/F/src/fsw-align-01.S"
     };
 
+  string arch32d[] = '{
+    `RISCVARCHTEST,
+    "rv32i_m/D/src/fadd.d_b10-01.S",
+    "rv32i_m/D/src/fadd.d_b1-01.S",
+    "rv32i_m/D/src/fadd.d_b11-01.S",
+    "rv32i_m/D/src/fadd.d_b12-01.S",
+    "rv32i_m/D/src/fadd.d_b13-01.S",
+    "rv32i_m/D/src/fadd.d_b2-01.S",
+    "rv32i_m/D/src/fadd.d_b3-01.S",
+    "rv32i_m/D/src/fadd.d_b4-01.S",
+    "rv32i_m/D/src/fadd.d_b5-01.S",
+    "rv32i_m/D/src/fadd.d_b7-01.S",
+    "rv32i_m/D/src/fadd.d_b8-01.S",
+    "rv32i_m/D/src/fclass.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b1-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b22-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b23-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b24-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b27-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b28-01.S",
+    "rv32i_m/D/src/fcvt.d.s_b29-01.S",
+    "rv32i_m/D/src/fcvt.d.w_b25-01.S",
+    "rv32i_m/D/src/fcvt.d.w_b26-01.S",
+    "rv32i_m/D/src/fcvt.d.wu_b25-01.S",
+    "rv32i_m/D/src/fcvt.d.wu_b26-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b22-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b23-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b24-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b27-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b28-01.S",
+    "rv32i_m/D/src/fcvt.s.d_b29-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b22-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b23-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b24-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b27-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b28-01.S",
+    "rv32i_m/D/src/fcvt.w.d_b29-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b1-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b22-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b23-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b24-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b27-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b28-01.S",
+    "rv32i_m/D/src/fcvt.wu.d_b29-01.S",
+    "rv32i_m/D/src/fdiv.d_b1-01.S",
+    "rv32i_m/D/src/fdiv.d_b20-01.S",
+    "rv32i_m/D/src/fdiv.d_b2-01.S",
+    "rv32i_m/D/src/fdiv.d_b21-01.S",
+    "rv32i_m/D/src/fdiv.d_b3-01.S",
+    "rv32i_m/D/src/fdiv.d_b4-01.S",
+    "rv32i_m/D/src/fdiv.d_b5-01.S",
+    "rv32i_m/D/src/fdiv.d_b6-01.S",
+    "rv32i_m/D/src/fdiv.d_b7-01.S",
+    "rv32i_m/D/src/fdiv.d_b8-01.S",
+    "rv32i_m/D/src/fdiv.d_b9-01.S",
+    "rv32i_m/D/src/feq.d_b1-01.S",
+    "rv32i_m/D/src/feq.d_b19-01.S",
+    "rv32i_m/D/src/fle.d_b1-01.S",
+    "rv32i_m/D/src/fle.d_b19-01.S",
+    "rv32i_m/D/src/flt.d_b1-01.S",
+    "rv32i_m/D/src/flt.d_b19-01.S",
+    // "rv32i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back
+    // "rv32i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266
+    "rv32i_m/D/src/fmadd.d_b14-01.S",
+    "rv32i_m/D/src/fmadd.d_b16-01.S",
+    "rv32i_m/D/src/fmadd.d_b17-01.S",
+    "rv32i_m/D/src/fmadd.d_b18-01.S",
+    "rv32i_m/D/src/fmadd.d_b2-01.S",
+    "rv32i_m/D/src/fmadd.d_b3-01.S",
+    "rv32i_m/D/src/fmadd.d_b4-01.S",
+    "rv32i_m/D/src/fmadd.d_b5-01.S",
+    "rv32i_m/D/src/fmadd.d_b6-01.S",
+    "rv32i_m/D/src/fmadd.d_b7-01.S",
+    "rv32i_m/D/src/fmadd.d_b8-01.S",
+    "rv32i_m/D/src/fmax.d_b1-01.S",
+    "rv32i_m/D/src/fmax.d_b19-01.S",
+    "rv32i_m/D/src/fmin.d_b1-01.S",
+    "rv32i_m/D/src/fmin.d_b19-01.S",
+    "rv32i_m/D/src/fmsub.d_b14-01.S",
+    "rv32i_m/D/src/fmsub.d_b16-01.S",
+    "rv32i_m/D/src/fmsub.d_b17-01.S",
+    "rv32i_m/D/src/fmsub.d_b18-01.S",
+    "rv32i_m/D/src/fmsub.d_b2-01.S",
+    "rv32i_m/D/src/fmsub.d_b3-01.S",
+    "rv32i_m/D/src/fmsub.d_b4-01.S",
+    "rv32i_m/D/src/fmsub.d_b5-01.S",
+    "rv32i_m/D/src/fmsub.d_b6-01.S",
+    "rv32i_m/D/src/fmsub.d_b7-01.S",
+    "rv32i_m/D/src/fmsub.d_b8-01.S",
+    "rv32i_m/D/src/fmul.d_b1-01.S",
+    "rv32i_m/D/src/fmul.d_b2-01.S",
+    "rv32i_m/D/src/fmul.d_b3-01.S",
+    "rv32i_m/D/src/fmul.d_b4-01.S",
+    "rv32i_m/D/src/fmul.d_b5-01.S",
+    "rv32i_m/D/src/fmul.d_b6-01.S",
+    "rv32i_m/D/src/fmul.d_b7-01.S",
+    "rv32i_m/D/src/fmul.d_b8-01.S",
+    "rv32i_m/D/src/fmul.d_b9-01.S",
+    "rv32i_m/D/src/fnmadd.d_b14-01.S",
+    "rv32i_m/D/src/fnmadd.d_b16-01.S",
+    "rv32i_m/D/src/fnmadd.d_b17-01.S",
+    "rv32i_m/D/src/fnmadd.d_b18-01.S",
+    "rv32i_m/D/src/fnmadd.d_b2-01.S",
+    "rv32i_m/D/src/fnmadd.d_b3-01.S",
+    "rv32i_m/D/src/fnmadd.d_b4-01.S",
+    "rv32i_m/D/src/fnmadd.d_b5-01.S",
+    "rv32i_m/D/src/fnmadd.d_b6-01.S",
+    "rv32i_m/D/src/fnmadd.d_b7-01.S",
+    "rv32i_m/D/src/fnmadd.d_b8-01.S",
+    "rv32i_m/D/src/fnmsub.d_b14-01.S",
+    "rv32i_m/D/src/fnmsub.d_b16-01.S",
+    "rv32i_m/D/src/fnmsub.d_b17-01.S",
+    "rv32i_m/D/src/fnmsub.d_b18-01.S",
+    "rv32i_m/D/src/fnmsub.d_b2-01.S",
+    "rv32i_m/D/src/fnmsub.d_b3-01.S",
+    "rv32i_m/D/src/fnmsub.d_b4-01.S",
+    "rv32i_m/D/src/fnmsub.d_b5-01.S",
+    "rv32i_m/D/src/fnmsub.d_b6-01.S",
+    "rv32i_m/D/src/fnmsub.d_b7-01.S",
+    "rv32i_m/D/src/fnmsub.d_b8-01.S",
+    "rv32i_m/D/src/fsgnj.d_b1-01.S",
+    "rv32i_m/D/src/fsgnjn.d_b1-01.S",
+    "rv32i_m/D/src/fsgnjx.d_b1-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b1-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b20-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b2-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b3-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b4-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b5-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b7-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b8-01.S",
+    // "rv32i_m/D/src/fsqrt.d_b9-01.S",
+    "rv32i_m/D/src/fssub.d_b10-01.S",
+    "rv32i_m/D/src/fssub.d_b1-01.S",
+    "rv32i_m/D/src/fssub.d_b11-01.S",
+    "rv32i_m/D/src/fssub.d_b12-01.S",
+    "rv32i_m/D/src/fssub.d_b13-01.S",
+    "rv32i_m/D/src/fssub.d_b2-01.S",
+    "rv32i_m/D/src/fssub.d_b3-01.S",
+    "rv32i_m/D/src/fssub.d_b4-01.S",
+    "rv32i_m/D/src/fssub.d_b5-01.S",
+    "rv32i_m/D/src/fssub.d_b7-01.S",
+    "rv32i_m/D/src/fssub.d_b8-01.S"
+};
+
 
   string arch32c[] = '{
     `RISCVARCHTEST,
@@ -1611,4 +1909,4 @@ string imperas32f[] = '{
  string wally32d[] = '{
     `WALLYTEST,
     "rv32i_m/D/src/WALLY-fld.S"
- };
\ No newline at end of file
+ };
diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index ddb62533..2490e564 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -51,7 +51,7 @@ lappend search_path ./mapped
 
 # Set up User Information
 set company "Oklahoma State University"
-set user    "James E. Stine"
+set user    "Prof. James E. Stine"
 
 # Alias
 alias ra report_area
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 9b72849f..ed43a1ab 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -27,7 +27,7 @@ set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
 
 eval file copy -force ${cfg} {$outputDir/hdl/}
-eval file copy -force ${cfg} $outputDir
+#eval file copy -force ${cfg} $outputDir
 eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/}
diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile
index e343d835..63f94900 100644
--- a/tests/riscof/Makefile
+++ b/tests/riscof/Makefile
@@ -6,16 +6,19 @@ arch_workdir = $(work)/riscv-arch-test
 wally_workdir = $(work)/wally-riscv-arch-test
 
 current_dir = $(shell pwd)
-XLEN    ?= 64
+#XLEN    ?= 64
 
-all: root build_rv32e build_wally build_arch 
+#all: root fsd_fld_tempfix arch32 wally32  wally32e arch64 wally64
+all: root fsd_fld_tempfix wally32
 
 root:
 	mkdir -p $(work_dir)
 	mkdir -p $(work)
 	mkdir -p $(arch_workdir)
 	mkdir -p $(wally_workdir)
-	sed 's,{0},$(current_dir),g;s,{1},$(XLEN)$(if $(findstring 64,$(XLEN)),gc,imc),g' config.ini > config$(XLEN).ini
+	sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini
+	sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
+	sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
 
 fsd_fld_tempfix:
     # this is a temporary fix, there's a typo on the rv64i_m/D/src/d_fsd-align-01.S and rv64i_m/D/src/d_fld-align-01.S tests
@@ -23,27 +26,30 @@ fsd_fld_tempfix:
 	find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*d_fld-align*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {}
 	find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*d_fsd-align*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {}
 
-build_arch: fsd_fld_tempfix
-	riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
-# rm -rf $(arch_workdir)/rv$(XLEN)i_m
-	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
-	rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
+arch32:
+	riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
+	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed"
 
-build_wally:
-	riscof run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
-# riscof --verbose debug run --work-dir=$(work_dir) --config=config$(XLEN).ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
-# rm -rf $(wally_workdir)/rv$(XLEN)i_m
-# mv -f $(work_dir)/rv$(XLEN)i_m $(wally_workdir)/
-	rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
-	rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv$(XLEN)i_m/ || echo "error suppressed"
+arch64:
+	riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser
+	rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"
+#	 Also copy F and D tests to RV64
+	rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed"  
 
-build_rv32e:
-	sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
+wally32:
+	riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
+	rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
+
+wally64:
+	riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
+	rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed"
+
+wally32e:
 	riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run
-# riscof --verbose debug run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run 2>&1 | tee log.txt
 	rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed"
 	rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed"
 
+
 memfile: 
 	find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done
 	find $(work) -type f -name "*.elf" | grep "rv32i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done
@@ -55,4 +61,4 @@ clean:
 	rm -f config32e.ini
 	rm -rf $(work_dir)
 	rm -rf $(wally_workdir)
-	rm -rf $(arch_workdir)
\ No newline at end of file
+	rm -rf $(arch_workdir)
diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py
index 9831e516..aa32757c 100644
--- a/tests/riscof/sail_cSim/riscof_sail_cSim.py
+++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py
@@ -127,4 +127,6 @@ class sail_cSim(pluginTemplate):
             execute+=coverage_cmd
 
             make.add_target(execute)
-        make.execute_all(self.work_dir)
+#        make.execute_all(self.work_dir)
+# DH 7/26/22 increase timeout so sim will finish on slow machines
+        make.execute_all(self.work_dir, timeout = 1800)
diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py
index 4f74c72f..d7d65c0b 100644
--- a/tests/riscof/spike/riscof_spike.py
+++ b/tests/riscof/spike/riscof_spike.py
@@ -180,7 +180,10 @@ class spike(pluginTemplate):
 
       # once the make-targets are done and the makefile has been created, run all the targets in
       # parallel using the make command set above.
-      make.execute_all(self.work_dir)
+      #make.execute_all(self.work_dir)
+      # DH 7/26/22 increase timeout to 1800 seconds so sim will finish on slow machines
+      make.execute_all(self.work_dir, timeout = 1800) 
+
 
       # if target runs are not required then we simply exit as this point after running all
       # the makefile targets.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output
index cfe54cb1..7b4c916c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output
@@ -16,6 +16,12 @@
 0000007F
 00000101 # Transmit 8 bits
 ffffff80
+00000101 # Odd parity
+00000079
+00000101 # Even parity
+0000006A
+00000101 # Extra stop bit
+0000005B
 00000002 # Transmission interrupt tests
 00000401 # Interrupt generated by finished transmission
 00000004
@@ -51,5 +57,19 @@ ffffffC1
 0000C101
 ffffffC1
 00000060
-
+ffffffC1 # FIFO filling/overrun test
+0000C401 # Threshold = 1
+ffffffC1 # Threshold = 4
+0000C101
+0000C401
+ffffffC1 # Threshold = 8
+0000C101
+0000C401
+ffffffC1 # Threshold = 14
+0000C101
+0000C401
+0000C101
+00000061 # FIFO has data, no overrun
+00000006 # wait for interrupt
+ffffffA3 # FIFO overrun error
 0000000b # ecall from test termination
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index e69b54f9..7146e833 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -1061,6 +1061,7 @@ uart_lsr_intr_loop:
     lb t3, 0(t2)
     andi t3, t3, 0x7
     bne t3, t4, uart_lsr_intr_loop
+uart_save_iir_status:
     sw t3, 0(t1)
     addi t1, t1, 4
     addi a6, a6, 4
@@ -1071,9 +1072,9 @@ uart_data_wait:
     li t3, 0x10000002 // IIR
     li a4, 0x61
 uart_read_LSR_IIR:
-    lb t4, 0(t3) // save IIR before potential clear
-    lb t5, 0(t2)
-    andi t6, t5, 0x61  // only care if all transmissions are done
+    lb t4, 0(t3) // save IIR before reading LSR mgith clear it
+    lb t5, 0(t2) // read LSR
+    andi t6, t5, 0x61  // wait until all transmissions are done and data is ready
     bne a4, t6, uart_read_LSR_IIR
 
 uart_data_ready:
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
index cf430cb4..deba11c2 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S
@@ -71,14 +71,14 @@ test_cases:
 
 .4byte UART_IER, 0x00, read08_test
 .4byte UART_IIR, 0x01, read08_test # IIR resets to 1
-# .4byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3
+# .4byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3 to help Linux boot
 .4byte UART_MCR, 0x00, read08_test
 .4byte UART_LSR, 0x60, read08_test # LSR resets with transmit status bits set
 .4byte UART_MSR, 0x00, read04_test
 
 # =========== Basic read-write ===========
 
-.4byte UART_LCR, 0x00, write08_test # set LCR to reset value *** remove if UART resets to correct value
+.4byte UART_LCR, 0x00, write08_test # set LCR to initial value
 .4byte UART_MCR, 0x10, write08_test # put UART into loopback for MSR test
 .4byte UART_LSR, 0x60, read08_test
 .4byte UART_THR, 0x00, write08_test # write value to UART
@@ -112,23 +112,45 @@ test_cases:
 
 # Transmit 8 bits
 
-.4byte UART_LCR, 0x03, write08_test # set LCR to transmit seven bits
+.4byte UART_LCR, 0x03, write08_test # set LCR to transmit eight bits
 .4byte UART_THR, 0x80, write08_test # write value to UART
 .4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
 .4byte UART_RBR, 0x80, read08_test  # read full written value + sign extension
 
+# Check function with odd parity
+
+.4byte UART_LCR, 0x0B, write08_test # set LCR to transmit 8 bits + odd partiy
+.4byte UART_THR, 0x79, write08_test # write value to UART
+.4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
+.4byte UART_RBR, 0x79, read08_test  # read full written value
+
+# Check function with even parity
+
+.4byte UART_LCR, 0x1B, write08_test # set LCR to transmit 8 bits + even parity
+.4byte UART_THR, 0x6A, write08_test # write value to UART
+.4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
+.4byte UART_RBR, 0x6A, read08_test  # read full written value
+
+# Check function with extra stop bit
+
+.4byte UART_LCR, 0x07, write08_test # set LCR to transmit 8 bits + extra stop
+.4byte UART_THR, 0x5B, write08_test # write value to UART
+.4byte 0x0, 0x0101, uart_data_wait  # wait for data to become ready then output IIR and then LSR
+.4byte UART_RBR, 0x5B, read08_test  # read full written value
+.4byte UART_LCR, 0x03, write08_test # set LCR to transmit 8 bits + no extra stop bit
+
 # =========== Transmit-related interrupts ===========
 
-.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts
-.4byte UART_IIR, 0x02, read08_test  # buffer should be empty, causing interrupt
-.4byte UART_THR, 0x00, write08_test # write zeroes to transmitter
-.4byte 0x0, 0x0401, uart_data_wait  # IIR should have data ready interrupt
-.4byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer
-.4byte UART_IIR, 0x04, read08_test  # data interrupt should still be high
-.4byte 0x0, 0x06, uart_lsr_intr_wait     # wait for transmission to complete, IIR should throw error due to overrun error.
-.4byte UART_LSR, 0x63, read08_test  # read overrun error from LSR
-.4byte UART_IIR, 0x04, read08_test  # check that LSR interrupt was cleared
-.4byte UART_RBR, 0x01, read08_test  # read previous value from UART
+.4byte UART_IER, 0x07, write08_test     # enable data available, buffer empty, and line status interrupts
+.4byte UART_IIR, 0x02, read08_test      # buffer should be empty, causing interrupt
+.4byte UART_THR, 0x00, write08_test     # write zeroes to transmitter
+.4byte 0x0, 0x0401, uart_data_wait      # IIR should have data ready interrupt
+.4byte UART_THR, 0x01, write08_test     # write 1 to transmitter buffer
+.4byte UART_IIR, 0x04, read08_test      # data interrupt should still be high
+.4byte 0x0, 0x06, uart_lsr_intr_wait    # wait for transmission to complete, IIR should throw error due to overrun error.
+.4byte UART_LSR, 0x23, read08_test      # read overrun error from LSR
+.4byte UART_IIR, 0x04, read08_test      # check that LSR interrupt was cleared
+.4byte UART_RBR, 0x01, read08_test      # read previous value from UART
 
 # =========== MODEM interrupts ===========
 
@@ -183,5 +205,44 @@ test_cases:
 .4byte UART_FCR, 0xC1, read08_test  # Check that FCR clears bits 1 and 2 when written to 1
 .4byte UART_LSR, 0x60, read08_test  # No data ready, FIFO cleared by writing to FCR
 
+# =========== FIFO receiver/overrun ===========
+
+.4byte UART_FCR, 0x01, write08_test # Set FIFO trigger threshold to 1 and enable FIFO mode
+.4byte UART_IIR, 0xC1, read08_test  # FIFO has not reached trigger level
+.4byte UART_THR, 0x00, write08_test # Write 0 to transmit register
+.4byte 0x0, 0xC401, uart_data_wait  # Interrupt due to trigger threshold reached
+.4byte UART_FCR, 0x41, write08_test # Set FIFO trigger threshold to 4
+.4byte UART_IIR, 0xC1, read08_test  # FIFO has not reached trigger threshold
+.4byte UART_THR, 0x01, write08_test # Write 1 to transmit register
+.4byte UART_THR, 0x02, write08_test # Write 2 to transmit register
+.4byte 0x0, 0xC101, uart_data_wait  # FIFO has not reached trigger threshold
+.4byte UART_THR, 0x03, write08_test # Write 3 to transmit register
+.4byte 0x0, 0xC401, uart_data_wait  # Interrupt due to trigger threshold reached
+.4byte UART_FCR, 0x81, write08_test # Set FIFO trigger threshold to 8
+.4byte UART_IIR, 0xC1, read08_test  # FIFO has not reached trigger threshold
+.4byte UART_THR, 0x04, write08_test # Write 4 to transmit register
+.4byte UART_THR, 0x05, write08_test # Write 5 to transmit register
+.4byte UART_THR, 0x06, write08_test # Write 6 to transmit register
+.4byte 0x0, 0xC101, uart_data_wait  # FIFO has not reached trigger threshold
+.4byte UART_THR, 0x07, write08_test # Write 7 to transmit register
+.4byte 0x0, 0xC401, uart_data_wait  # Interrupt due to trigger threshold reached
+.4byte UART_FCR, 0xC1, write08_test # Set FIFO trigger threshold to 14
+.4byte UART_IIR, 0xC1, read08_test  # FIFO has not reached trigger threshold
+.4byte UART_THR, 0x08, write08_test # Write 8 to transmit register
+.4byte UART_THR, 0x09, write08_test # Write 9 to transmit register
+.4byte UART_THR, 0x0A, write08_test # Write 10 to transmit register
+.4byte UART_THR, 0x0B, write08_test # Write 11 to transmit register
+.4byte UART_THR, 0x0C, write08_test # Write 12 to transmit register
+.4byte 0x0, 0xC101, uart_data_wait  # FIFO has not reached trigger threshold
+.4byte UART_THR, 0x0D, write08_test # Write 13 to transmit register
+.4byte 0x0, 0xC401, uart_data_wait  # Interrupt due to trigger threshold reached
+.4byte UART_THR, 0x0E, write08_test # Write 14 to transmit register
+.4byte UART_THR, 0x0F, write08_test # Write 15 to transmit register
+.4byte 0x0, 0xC101, uart_data_wait
+.4byte UART_LSR, 0x61, read08_test      # FIFO contains data, no overrun error
+.4byte UART_THR, 0x10, write08_test     # Write 16 to transmit register, filling RX shift register
+.4byte UART_THR, 0x11, write08_test     # Write 17 to transmit register, destroying contents held in shift register
+.4byte 0x0, 0x06, uart_lsr_intr_wait    # Wait for LSR interrupt ID
+.4byte UART_LSR, 0xA3, read08_test      # Read overrun error from LSR
 
 .4byte 0x0, 0x0, terminate_test
\ No newline at end of file