From 0123776037b24f172ab6cb2fa6702117e8f9d422 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 20 Jan 2023 15:01:54 -0600 Subject: [PATCH] Updated figure cache references. --- pipelined/src/cache/cache.sv | 2 +- pipelined/src/cache/cacheLRU.sv | 2 +- pipelined/src/cache/cachefsm.sv | 2 +- pipelined/src/cache/cacheway.sv | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 4761241d..72b97a31 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -7,7 +7,7 @@ // // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.11, and 7.20) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19) // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/cache/cacheLRU.sv b/pipelined/src/cache/cacheLRU.sv index 8dfce679..be42036e 100644 --- a/pipelined/src/cache/cacheLRU.sv +++ b/pipelined/src/cache/cacheLRU.sv @@ -7,7 +7,7 @@ // // Purpose: Implements Pseudo LRU. Tested for Powers of 2. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.16 to 7.19) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18) // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 2f9bca06..bc9982e5 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -7,7 +7,7 @@ // // Purpose: Controller for the dcache fsm // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.15 and Table 7.1) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index d5fc0b7d..d3e99672 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -7,7 +7,7 @@ // // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. // -// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.12) +// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11) // // A component of the CORE-V-WALLY configurable RISC-V project. //