diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index bd1caa9f..ccdead7d 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -31,7 +31,7 @@
 `include "wally-config.vh"
 
 package ahbliteState;
-  typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE, MMUIDLE} statetype;
+  typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADC, ATOMICREAD, ATOMICWRITE, MMUTRANSLATE} statetype;
 endpackage
 
 module ahblite (
@@ -56,6 +56,8 @@ module ahblite (
   input  logic             MMUTranslate, MMUTranslationComplete,
   output logic [`XLEN-1:0] MMUReadPTE,
   output logic             MMUReady,
+  // Signals from PMA checker
+  input  logic             SquashAHBAccess,
   // Return from bus
   output logic [`XLEN-1:0] ReadDataW,
   // AHB-Lite external signals
@@ -103,6 +105,10 @@ module ahblite (
 
   flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState);
 
+  // *** If the SquashAHBAccess signal is high, we need to set NextBusState to IDLE.
+  // We could either have this case statement set a signal ProposedNextBusState, which gets
+  // used for NextBusState when we are not squashing. Alternatively, we could add a bunch of
+  // conditional statments below 
   always_comb 
     case (BusState) 
       IDLE: if      (MMUTranslate) NextBusState = MMUTRANSLATE;