From 00b3e36b30ce995213e4029a3fbc824804ed4ed4 Mon Sep 17 00:00:00 2001 From: Thomas Fleming Date: Thu, 22 Apr 2021 01:52:43 -0400 Subject: [PATCH] Refactor tlb_ram to use flop primitives --- wally-pipelined/src/mmu/tlb_ram.sv | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/src/mmu/tlb_ram.sv b/wally-pipelined/src/mmu/tlb_ram.sv index 7e24a0a2..9c281d2d 100644 --- a/wally-pipelined/src/mmu/tlb_ram.sv +++ b/wally-pipelined/src/mmu/tlb_ram.sv @@ -28,7 +28,6 @@ `include "wally-config.vh" `include "wally-constants.vh" -// *** use actual flop notation instead of initialbegin and alwaysff module tlb_ram #(parameter ENTRY_BITS = 3) ( input clk, reset, input [ENTRY_BITS-1:0] VPNIndex, // Index to read from @@ -44,17 +43,22 @@ module tlb_ram #(parameter ENTRY_BITS = 3) ( logic [`XLEN-1:0] ram [0:NENTRIES-1]; logic [`XLEN-1:0] PageTableEntry; - always @(posedge clk) begin - if (TLBWrite) ram[WriteIndex] <= PageTableEntryWrite; - end + + logic [NENTRIES-1:0] RAMEntryWrite; + + decoder #(ENTRY_BITS) tlb_ram_decoder(WriteIndex, RAMEntryWrite); + + // Generate a flop for every entry in the RAM + generate + genvar i; + for (i = 0; i < NENTRIES; i++) begin: tlb_ram_flops + flopenr #(`XLEN) pte_flop(clk, reset, RAMEntryWrite[i] & TLBWrite, + PageTableEntryWrite, ram[i]); + end + endgenerate assign PageTableEntry = ram[VPNIndex]; assign PTEAccessBits = PageTableEntry[7:0]; assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10]; - initial begin - for (int i = 0; i < NENTRIES; i++) - ram[i] = `XLEN'b0; - end - endmodule