From 002c32d2ad0ae2a43a0cfe58eee6ee35a22c9228 Mon Sep 17 00:00:00 2001
From: Ross Thompson <stephen.thompson.37@us.af.mil>
Date: Wed, 30 Jun 2021 17:02:36 -0500
Subject: [PATCH] The icache ptw interlock is actually correct now. There
needed to be a 1 cycle delay.
---
wally-pipelined/regression/wave.do | 4 +-
wally-pipelined/src/cache/ICacheCntrl.sv | 7 +++-
wally-pipelined/src/mmu/pagetablewalker.sv | 48 +++++++++++++---------
3 files changed, 37 insertions(+), 22 deletions(-)
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index eef15339..4669e48c 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -351,7 +351,7 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genb
add wave -noupdate -expand -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 5} {11172515 ns} 0} {{Cursor 8} {2967 ns} 0}
+WaveRestoreCursors {{Cursor 5} {11172515 ns} 0} {{Cursor 8} {3207 ns} 0}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 189
@@ -367,4 +367,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {2729 ns} {3045 ns}
+WaveRestoreZoom {2930 ns} {3454 ns}
diff --git a/wally-pipelined/src/cache/ICacheCntrl.sv b/wally-pipelined/src/cache/ICacheCntrl.sv
index 78bdb46a..bc5c30b3 100644
--- a/wally-pipelined/src/cache/ICacheCntrl.sv
+++ b/wally-pipelined/src/cache/ICacheCntrl.sv
@@ -112,6 +112,8 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
localparam STATE_INVALIDATE = 18; // *** not sure if invalidate or evict? invalidate by cache block or address?
localparam STATE_TLB_MISS = 19;
+ localparam STATE_TLB_MISS_DONE = 20;
+
localparam AHBByteLength = `XLEN / 8;
@@ -371,11 +373,14 @@ module ICacheCntrl #(parameter BLOCKLEN = 256) (
end
STATE_TLB_MISS: begin
if (ITLBWriteF) begin
- NextState = STATE_READY;
+ NextState = STATE_TLB_MISS_DONE;
end else begin
NextState = STATE_TLB_MISS;
end
end
+ STATE_TLB_MISS_DONE : begin
+ NextState = STATE_READY;
+ end
default: begin
PCMux = 2'b01;
NextState = STATE_READY;
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index f0f30301..e917e83c 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -96,7 +96,25 @@ module pagetablewalker (
// Outputs of walker
logic [`XLEN-1:0] PageTableEntry;
logic [1:0] PageType;
+ logic StartWalk;
+ logic EndWalk;
+
+ typedef enum {LEVEL0_WDV,
+ LEVEL0,
+ LEVEL1_WDV,
+ LEVEL1,
+ LEVEL2_WDV,
+ LEVEL2,
+ LEVEL3_WDV,
+ LEVEL3,
+ LEAF,
+ IDLE,
+ FAULT} statetype;
+ statetype WalkerState, NextWalkerState;
+
+ logic PRegEn;
+
assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
@@ -108,23 +126,30 @@ module pagetablewalker (
flopenr #(`XLEN)
TranslationVAdrReg(.clk(clk),
.reset(reset),
- .en(1'b1), // *** use enable later to save power
+ .en(StartWalk), // *** use enable later to save power
.d(TranslationVAdr),
.q(TranslationVAdrQ));
- flopr #(1)
+ flopenrc #(1)
DTLBMissMReg(.clk(clk),
.reset(reset),
+ .en(StartWalk | EndWalk),
+ .clear(EndWalk),
.d(DTLBMissM),
.q(DTLBMissMQ));
- flopr #(1)
+ flopenrc #(1)
ITLBMissMReg(.clk(clk),
.reset(reset),
+ .en(StartWalk | EndWalk),
+ .clear(EndWalk),
.d(ITLBMissF),
.q(ITLBMissFQ));
-
+
+ assign StartWalk = WalkerState == IDLE && (DTLBMissM | ITLBMissF);
+ assign EndWalk = WalkerState == LEAF;
+
assign MMUTranslate = DTLBMissMQ | ITLBMissFQ;
//assign MMUTranslate = DTLBMissM | ITLBMissF;
@@ -143,21 +168,6 @@ module pagetablewalker (
assign PageTypeF = PageType;
assign PageTypeM = PageType;
- typedef enum {LEVEL0_WDV,
- LEVEL0,
- LEVEL1_WDV,
- LEVEL1,
- LEVEL2_WDV,
- LEVEL2,
- LEVEL3_WDV,
- LEVEL3,
- LEAF,
- IDLE,
- FAULT} statetype;
-
- statetype WalkerState, NextWalkerState;
-
- logic PRegEn;
generate
if (`XLEN == 32) begin