Added Template Makefile
This Makefile will be used as a way to start new projects with the same hierarchy. It will also be tightly coupled with the x testing framework for c (x_tfw4c). It has targets to setup the source, include, object, and tests directories using the `make dirs` command. There is some fun interesting things that I used to get the target to recompile when the header files are updated using the -MMD and -MP flags in gcc. These flags basically allow for the generation of dependencies from each source file that are exported and then included using the -include $(DEPENDENCIES) line at the bottem of the Makefile.
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c_projects/x_tfw4c/Makefile
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c_projects/x_tfw4c/Makefile
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# MakeFile for placeholder
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# Created mm/dd/yyyy
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# Authored by: xavi
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# ----------------------
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# | THIS IS A TEMPLATE |
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# ----------------------
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# TODO:
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# %s/placeholder/project_name/g
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# Change date file was created to today
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# run make dirs to create project hierarchy
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# Place headers in include and source files in src
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# Delete this text
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.POSIX:
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# DIRECTORIES
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SRC_DIR := src
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INCLUDE_DIR := include
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OBJ_DIR := obj
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TESTS_DIR := tests
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# C compiler settings
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CC := gcc
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CFLAGS := -ggdb -I$(INCLUDE_DIR) -Wall -Wextra -MMD -MP
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DFLAGS :=
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# Files
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SRC := $(wildcard $(SRC_DIR)/*.c)
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OBJ := $(SRC:$(SRC_DIR)/%.c=$(OBJ_DIR)/%.o)
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TESTS := $(wildcard $(TESTS_DIR)/*.c)
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# Get Dependencies from gcc using -MMD and -MP
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DEPENDENCIES := $(OBJ:%.o=%.d)
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# Final Binary Name
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PROJECT_NAME := placeholder
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all: $(PROJECT_NAME)
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$(TESTS:$(TESTS_DIR)/%.c=%): $(OBJ)
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$(CC) $(CFLAGS) $(DFLAGS) -o $(@) $(^)
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$(PROJECT_NAME): $(OBJ)
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$(CC) $(CFLAGS) $(DFLAGS) -o $(@) $(^)
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$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
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$(CC) $(CFLAGS) $(DFLAGS) -c -o $(@) $(<)
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clean:
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rm -f $(PROJECT_NAME) $(OBJ_DIR)/* $(TESTS:$(TESTS_DIR)/%.c=%)
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-include $(DEPENDENCIES)
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.PHONY: clean all
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# Create Project Hierarchy
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dirs: $(SRC_DIR) $(OBJ_DIR) $(TESTS_DIR) $(INCLUDE_DIR)
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$(SRC_DIR) $(OBJ_DIR) $(TESTS_DIR) $(INCLUDE_DIR):
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mkdir -p $(@)
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