Added Template Makefile

This Makefile will be used as a way to start new projects with the same
hierarchy. It will also be tightly coupled with the x testing framework
for c (x_tfw4c).

It has targets to setup the source, include, object, and tests
directories using the `make dirs` command.

There is some fun interesting things that I used to get the target to
recompile when the header files are updated using the -MMD and -MP flags
in gcc.

These flags basically allow for the generation of dependencies from each
source file that are exported and then included using the -include
$(DEPENDENCIES) line at the bottem of the Makefile.
This commit is contained in:
xavi 2025-12-17 17:26:21 -08:00
parent 0c834ca675
commit a4eb8224a8

View File

@ -0,0 +1,67 @@
# MakeFile for placeholder
# Created mm/dd/yyyy
# Authored by: xavi
# ----------------------
# | THIS IS A TEMPLATE |
# ----------------------
# TODO:
# %s/placeholder/project_name/g
# Change date file was created to today
# run make dirs to create project hierarchy
# Place headers in include and source files in src
# Delete this text
.POSIX:
# DIRECTORIES
SRC_DIR := src
INCLUDE_DIR := include
OBJ_DIR := obj
TESTS_DIR := tests
# C compiler settings
CC := gcc
CFLAGS := -ggdb -I$(INCLUDE_DIR) -Wall -Wextra -MMD -MP
DFLAGS :=
# Files
SRC := $(wildcard $(SRC_DIR)/*.c)
OBJ := $(SRC:$(SRC_DIR)/%.c=$(OBJ_DIR)/%.o)
TESTS := $(wildcard $(TESTS_DIR)/*.c)
# Get Dependencies from gcc using -MMD and -MP
DEPENDENCIES := $(OBJ:%.o=%.d)
# Final Binary Name
PROJECT_NAME := placeholder
all: $(PROJECT_NAME)
$(TESTS:$(TESTS_DIR)/%.c=%): $(OBJ)
$(CC) $(CFLAGS) $(DFLAGS) -o $(@) $(^)
$(PROJECT_NAME): $(OBJ)
$(CC) $(CFLAGS) $(DFLAGS) -o $(@) $(^)
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(CFLAGS) $(DFLAGS) -c -o $(@) $(<)
clean:
rm -f $(PROJECT_NAME) $(OBJ_DIR)/* $(TESTS:$(TESTS_DIR)/%.c=%)
-include $(DEPENDENCIES)
.PHONY: clean all
# Create Project Hierarchy
dirs: $(SRC_DIR) $(OBJ_DIR) $(TESTS_DIR) $(INCLUDE_DIR)
$(SRC_DIR) $(OBJ_DIR) $(TESTS_DIR) $(INCLUDE_DIR):
mkdir -p $(@)