mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
147 lines
4.9 KiB
Plaintext
147 lines
4.9 KiB
Plaintext
# imperas.ic
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# Initialization file for ImperasDV lock step simulation
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# David_Harris@hmc.edu 15 August 2024
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#--mpdconsole
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#--gdbconsole
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#--showoverrides
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#--showcommands
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# Core settings
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--variant RV32GCK # for RV32GC
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--override cpu/priv_version=1.12
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--override cpu/user_version=20191213
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# arch
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--override cpu/mimpid=0x100
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--override cpu/mvendorid=0x602
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--override cpu/marchid=0x24
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--override refRoot/cpu/tvec_align=64
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--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written
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# bit manipulation
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--override cpu/add_Extensions=B
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--override cpu/bitmanip_version=1.0.0
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--override cpu/misa_B_Zba_Zbb_Zbs=T
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# More extensions
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--override cpu/Zcb=T
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--override cpu/Zicond=T
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--override cpu/Zfh=T
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--override cpu/Zfa=T
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# Cache block operations
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--override cpu/Zicbom=T
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--override cpu/Zicbop=T
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--override cpu/Zicboz=T
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--override cmomp_bytes=64 # Zic64b
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--override cmoz_bytes=64 # Zic64b
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--override lr_sc_grain=4 # Za64rs requires <=64; we use native word size
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# 64 KiB continuous huge pages supported
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#--override cpu/Svpbmt=F
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#--override cpu/Svnapot_page_mask=65536
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# SV32 supported
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--override cpu/Sv_modes=3
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#--showoverrides
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--override cpu/Svinval=T
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# clarify
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#--override refRoot/cpu/mtvec_sext=F
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--override cpu/tval_ii_code=T
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#--override cpu/time_undefined=T
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#--override cpu/cycle_undefined=T
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#--override cpu/instret_undefined=T
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#--override cpu/hpmcounter_undefined=T
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# context registers not implemented
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#--override cpu/scontext_undefined=True
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#--override cpu/mcontext_undefined=True
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# Disable all features that might want mseccfg or CSRs 7a0-7af
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--override cpu/Smepmp_version=none
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--override cpu/Smmpm=none
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#--override cpu/Zicfilp=F
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--override cpu/trigger_num=0 # disable CSRs 7a0-7a8
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# For code coverage, don't produce pseudoinstructions
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--override no_pseudo_inst=T
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# Show "c." with compressed instructions
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--override show_c_prefix=T
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# nonratified mnoise register not implemented
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--override cpu/mnoise_undefined=T
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# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
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#--override cpu/ecode_mask=0x8000000F # for RV32
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--override cpu/ecode_mask=0x800000000000000F # for RV64
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# Debug mode not yet supported
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--override cpu/debug_mode=none
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# Zkr entropy source and seed register not supported.
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--override cpu/Zkr=F
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# ShangMi Crypto not supported
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--override cpu/Zksed=F
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--override cpu/Zksh=F
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--override cpu/reset_address=0x80000000
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--override cpu/unaligned=F # Zicclsm (should be true)
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--override cpu/ignore_non_leaf_DAU=1
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--override cpu/wfi_is_nop=T
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--override cpu/misa_Extensions_mask=0x0 # MISA not writable
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--override cpu/Sstc=T
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# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1
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--override cpu/Svadu=T
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#--override cpu/updatePTEA=F
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#--override cpu/updatePTED=F
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--override cpu/PMP_registers=16
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--override cpu/PMP_undefined=T
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# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception
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--override cpu/mstatus_fs_mode=write_1
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# PMA Settings
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# 'r': read access allowed
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# 'w': write access allowed
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# 'x': execute access allowed
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# 'a': aligned access required
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# 'A': atomic instructions NOT allowed (actually USER1 privilege needed)
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# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed)
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# '1': 1-byte accesses allowed
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# '2': 2-byte accesses allowed
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# '4': 4-byte accesses allowed
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# '8': 8-byte accesses allowed
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# '-', space: ignored (use for input string formatting).
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#
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# SVxx Memory 0x0000000000 0x7FFFFFFFFF
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#
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--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise
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--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
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--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
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--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
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--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT
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--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC
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--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF
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--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF
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--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF
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--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM
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# Enable the Imperas instruction coverage
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#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0
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#-override refRoot/cpu/cv/cover=basic
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#-override refRoot/cpu/cv/extensions=RV32I
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# Store simulator output to logfile
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--output imperas.log
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