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https://github.com/openhwgroup/cvw
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96 lines
4.0 KiB
Systemverilog
96 lines
4.0 KiB
Systemverilog
///////////////////////////////////////////
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// mul.sv
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//
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// Written: David_Harris@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Multiply instructions
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module mul (
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// Execute Stage interface
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input logic clk, reset,
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input logic StallM, FlushM,
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input logic [`XLEN-1:0] SrcAE, SrcBE,
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input logic [2:0] Funct3E,
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output logic [`XLEN*2-1:0] ProdM
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);
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// Number systems
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// Let A' = sum(i=0, XLEN-2, A[i]*2^i)
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// Unsigned: A = A' + A[XLEN-1]*2^(XLEN-1)
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// Signed: A = A' - A[XLEN-1]*2^(XLEN-1)
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// Multiplication: A*B
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// Let P' = A' * B'
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// PA = (A' * B[XLEN-1])
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// PB = (B' * A[XLEN-1])
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// PP = A[XLEN-1] * B[XLEN-1]
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// Signed * Signed = P' + (-PA - PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
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// Signed * Unsigned = P' + ( PA - PB)*2^(XLEN-1) - PP*2^(2XLEN-2)
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// Unsigned * Unsigned = P' + ( PA + PB)*2^(XLEN-1) + PP*2^(2XLEN-2)
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logic [`XLEN*2-1:0] PP0E, PP1E, PP2E, PP3E, PP4E;
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logic [`XLEN*2-1:0] PP0M, PP1M, PP2M, PP3M, PP4M;
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logic [`XLEN*2-1:0] Pprime;
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logic [`XLEN-2:0] PA, PB;
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logic PP;
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logic MULH, MULHSU, MULHU;
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logic [`XLEN-1:0] Aprime, Bprime;
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//////////////////////////////
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// Execute Stage: Compute partial products
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//////////////////////////////
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assign Aprime = {1'b0, SrcAE[`XLEN-2:0]};
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assign Bprime = {1'b0, SrcBE[`XLEN-2:0]};
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redundantmul #(`XLEN) bigmul(.a(Aprime), .b(Bprime), .out0(PP0E), .out1(PP1E));
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assign PA = {(`XLEN-1){SrcAE[`XLEN-1]}} & SrcBE[`XLEN-2:0];
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assign PB = {(`XLEN-1){SrcBE[`XLEN-1]}} & SrcAE[`XLEN-2:0];
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assign PP = SrcAE[`XLEN-1] & SrcBE[`XLEN-1];
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// flavor of multiplication
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assign MULH = (Funct3E == 3'b001);
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assign MULHSU = (Funct3E == 3'b010);
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// assign MULHU = (Funct3E == 2'b11); // signal unused
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// Handle signs
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assign PP2E = {2'b00, (MULH | MULHSU) ? ~PA : PA, {(`XLEN-1){1'b0}}};
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assign PP3E = {2'b00, (MULH) ? ~PB : PB, {(`XLEN-1){1'b0}}};
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always_comb
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if (MULH) PP4E = {1'b1, PP, {(`XLEN-3){1'b0}}, 1'b1, {(`XLEN){1'b0}}};
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else if (MULHSU) PP4E = {1'b1, ~PP, {(`XLEN-2){1'b0}}, 1'b1, {(`XLEN-1){1'b0}}};
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else PP4E = {1'b0, PP, {(`XLEN*2-2){1'b0}}};
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//////////////////////////////
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// Memory Stage: Sum partial proudcts
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//////////////////////////////
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flopenrc #(`XLEN*2) PP0Reg(clk, reset, FlushM, ~StallM, PP0E, PP0M);
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flopenrc #(`XLEN*2) PP1Reg(clk, reset, FlushM, ~StallM, PP1E, PP1M);
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flopenrc #(`XLEN*2) PP2Reg(clk, reset, FlushM, ~StallM, PP2E, PP2M);
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flopenrc #(`XLEN*2) PP3Reg(clk, reset, FlushM, ~StallM, PP3E, PP3M);
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flopenrc #(`XLEN*2) PP4Reg(clk, reset, FlushM, ~StallM, PP4E, PP4M);
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assign ProdM = PP0M + PP1M + PP2M + PP3M + PP4M; //SrcAE * SrcBE;
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endmodule
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