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108 lines
4.9 KiB
Systemverilog
108 lines
4.9 KiB
Systemverilog
///////////////////////////////////////////
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// alu.sv
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//
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// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
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// Created: 9 January 2021
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// Modified:
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//
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// Purpose: RISC-V Arithmetic/Logic Unit
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
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input logic [6:0] Funct7, // Funct7 from execute stage
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input logic [2:0] Funct3, // With ALUControl, indicates operation to perform
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output logic [WIDTH-1:0] Result, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic W64; // RV64 W-type instruction
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logic SubArith; // Performing subtraction or arithmetic right shift
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logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops
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logic Asign, Bsign; // Sign bits of A, B
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logic rotate;
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// Extract control signals from ALUControl.
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assign {W64, SubArith, ALUOp} = ALUControl;
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// Addition
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assign CondInvB = SubArith ? ~B : B;
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assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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// Shifts
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(rotate));
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// Condition code flags are based on subtraction output Sum = A-B.
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// Overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign of A.
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// LT is simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
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assign Neg = Sum[WIDTH-1];
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assign Asign = A[WIDTH-1];
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assign Bsign = B[WIDTH-1];
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg;
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assign LTU = ~Carry;
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// SLT
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assign SLT = {{(WIDTH-1){1'b0}}, LT};
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assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
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// Select appropriate ALU Result
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always_comb
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
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else casez (Funct3) // Otherwise check Funct3
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign ALUResult = FullResult;
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//NOTE: This looks good and can be merged.
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if (`ZBC_SUPPORTED) begin: zbc
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zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult));
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end else assign ZBCResult = 0;
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//NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU
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if (`ZBC_SUPPORTED) begin : zbcdecoder
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always_comb
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case ({Funct7, Funct3})
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10'b0000101_001: Result = ZBCResult;
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10'b0000101_011: Result = ZBCResult;
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10'b0000101_010: Result = ZBCResult;
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default: Result = ALUResult;
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endcase
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end else assign Result = ALUResult;
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endmodule |