Ross Thompson fea439b84d SDC to ABHLite interface partially done. ... Added SDC to adrdec and uncore.		2021-09-24 10:45:09 -05:00
..
cache	Fixed the amo on dcache miss cpu stall issue.	2021-09-17 22:15:03 -05:00
ebu	Additional cleanup of ahblite.	2021-08-25 22:53:20 -05:00
fpu	Modified rxfull determination in UART, started division	2021-09-12 20:00:24 -04:00
generic	Fixed bug with or_rows.	2021-09-11 15:51:11 -05:00
hazard	The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.	2021-09-17 10:33:57 -05:00
ieu	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
ifu	Updated Dcache to fully support flush. This appears to work.	2021-09-17 10:25:21 -05:00
lsu	Finished adding the d cache flush. Required ensuring the write data, address, and size are	2021-09-17 13:03:04 -05:00
mmu	SDC to ABHLite interface partially done.	2021-09-24 10:45:09 -05:00
muldiv	Restored old integer divider	2021-09-12 22:07:52 -04:00
privileged	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
sdc	SDC to ABHLite interface partially done.	2021-09-24 10:45:09 -05:00
uncore	SDC to ABHLite interface partially done.	2021-09-24 10:45:09 -05:00
wally	SDC to ABHLite interface partially done.	2021-09-24 10:45:09 -05:00