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166 lines
12 KiB
Systemverilog
166 lines
12 KiB
Systemverilog
///////////////////////////////////////////
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// privileged.sv
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//
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// Written: David_Harris@hmc.edu 5 January 2021
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// Modified:
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//
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// Purpose: Implements the CSRs, Exceptions, and Privileged operations
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// See RISC-V Privileged Mode Specification 20190608
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//
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// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.8)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module privileged (
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input logic clk, reset,
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input logic StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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// CSR Reads and Writes, and values needed for traps
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input logic CSRReadM, CSRWriteM, // Read or write CSRs
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input logic [`XLEN-1:0] SrcAM, // GPR register to write
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input logic [31:0] InstrM, // Instruction
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [`XLEN-1:0] IEUAdrM, // address from IEU
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input logic [`XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return PC logic
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// control signals
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input logic InstrValidM, // Current instruction is valid (not flushed)
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input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
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input logic PrivilegedM, // privileged instruction
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// processor events for performance counter logging
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input logic FRegWriteM, // instruction will write floating-point registers
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input logic LoadStallD, // load instruction is stalling
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input logic StoreStallD, // store instruction is stalling
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input logic ICacheStallF, // I cache stalled
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input logic DCacheStallM, // D cache stalled
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input logic BPDirPredWrongM, // branch predictor guessed wrong direction
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input logic BTAWrongM, // branch predictor guessed wrong target
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input logic RASPredPCWrongM, // return adddress stack guessed wrong target
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input logic IClassWrongM, // branch predictor guessed wrong instruction class
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input logic BPWrongM, // branch predictor is wrong
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input logic [3:0] InstrClassM, // actual instruction class
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input logic DCacheMiss, // data cache miss
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input logic DCacheAccess, // data cache accessed (hit or miss)
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input logic ICacheMiss, // instruction cache miss
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input logic ICacheAccess, // instruction cache access
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input logic DivBusyE, // integer divide busy
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input logic FDivBusyE, // floating point divide busy
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// fault sources
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input logic InstrAccessFaultF, // instruction access fault
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input logic LoadAccessFaultM, StoreAmoAccessFaultM, // load or store access fault
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input logic HPTWInstrAccessFaultF, // hardware page table access fault while fetching instruction PTE
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input logic InstrPageFaultF, // page faults
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input logic LoadPageFaultM, StoreAmoPageFaultM, // page faults
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input logic InstrMisalignedFaultM, // misaligned instruction fault
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input logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned data fault
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input logic IllegalIEUFPUInstrD, // illegal instruction from IEU or FPU
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input logic MTimerInt, MExtInt, SExtInt, MSwInt, // interrupt sources
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input logic [63:0] MTIME_CLINT, // timer value from CLINT
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input logic [4:0] SetFflagsM, // set FCSR flags from FPU
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input logic SelHPTW, // HPTW in use. Causes system to use S-mode endianness for accesses
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// CSR outputs
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output logic [`XLEN-1:0] CSRReadValW, // Value read from CSR
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output logic [1:0] PrivilegeModeW, // current privilege mode
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output logic [`XLEN-1:0] SATP_REGW, // supervisor address translation register
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output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // status register bits
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output logic [1:0] STATUS_MPP, STATUS_FS, // status register bits
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration entries to MMU
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output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU
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output logic [2:0] FRM_REGW, // FPU rounding mode
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// PC logic output in privileged unit
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output logic [`XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
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// control outputs
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output logic RetM, TrapM, // return instruction, or trap
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output logic sfencevmaM, // sfence.vma instruction
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input logic InvalidateICacheM, // fence instruction
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output logic BigEndianM, // Use big endian in current privilege mode
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// Fault outputs
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output logic BreakpointFaultM, EcallFaultM, // breakpoint and Ecall traps should retire
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output logic wfiM, IntPendingM // Stall in Memory stage for WFI until interrupt pending or timeout
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);
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logic [3:0] CauseM; // trap cause
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logic [15:0] MEDELEG_REGW; // exception delegation CSR
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logic [11:0] MIDELEG_REGW; // interrupt delegation CSR
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logic sretM, mretM; // supervisor / machine return instruction
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logic IllegalCSRAccessM; // Illegal access to CSR
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logic IllegalIEUFPUInstrM; // Illegal IEU or FPU instruction, delayed to Mem stage
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logic InstrPageFaultM; // Instruction page fault, delayed to Mem stage
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logic InstrAccessFaultM; // Instruction access fault, delayed to Mem stages
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logic IllegalInstrFaultM; // Illegal instruction fault
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logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; // Status bits needed within privileged unit
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logic STATUS_MIE, STATUS_SIE; // status bits: interrupt enables
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logic [11:0] MIP_REGW, MIE_REGW; // interrupt pending and enable bits
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logic [1:0] NextPrivilegeModeM; // next privilege mode based on trap or return
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logic DelegateM; // trap should be delegated
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logic InterruptM; // interrupt occuring
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logic ExceptionM; // Memory stage instruction caused a fault
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logic HPTWInstrAccessFaultM; // Hardware page table access fault while fetching instruction PTE
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// track the current privilege level
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privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM,
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.STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW);
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// decode privileged instructions
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privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]),
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.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
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.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
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.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .sfencevmaM);
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// Control and Status Registers
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csr csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
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.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
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.sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
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.IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
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.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
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.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
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.MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.SetFflagsM, .FRM_REGW,
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.CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
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// pipeline early-arriving trap sources
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privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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.InstrPageFaultF, .InstrAccessFaultF, .HPTWInstrAccessFaultF, .IllegalIEUFPUInstrD,
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.InstrPageFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalIEUFPUInstrM);
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// trap logic
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trap trap(.reset,
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.InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
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.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
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.LoadPageFaultM, .StoreAmoPageFaultM,
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.mretM, .sretM, .PrivilegeModeW,
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.MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
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.InstrValidM, .CommittedM, .CommittedF,
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.TrapM, .RetM, .wfiM, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
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endmodule
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