Ross Thompson 563980443a Merge branch 'main' into rvvi		2024-06-10 18:10:23 -07:00
..
artyddr3.ucf
constraints-ArtyA7.xdc	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
constraints-vcu108.xdc
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
marked_debug_all.txt	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
marked_debug_small.txt
marked_debug.txt
small-debug.xdc	Added new signals to ILA to debug the RVVI tracer.	2024-05-30 16:43:25 -05:00
vcu-small-debug.xdc