cvw/tests/coverage/priv.S
2023-03-31 08:37:16 -07:00

66 lines
1.8 KiB
ArmAsm

///////////////////////////////////////////
// priv.S
//
// Written: David_Harris@hmc.edu 23 March 2023
//
// Purpose: Test coverage for EBU
//
// A component of the CORE-V-WALLY configurable RISC-V project.
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the License); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an AS IS BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
// load code to initalize stack, handle interrupts, terminate
#include "WALLY-init-lib.h"
main:
# switch to supervisor mode
li a0, 1
ecall
# Test read to stimecmp fails when MCOUNTEREN_TM is not set
addi t0, zero, 0
csrr t0, stimecmp
# CSR coverage
csrw scause, zero
csrw stval, zero
csrw scounteren, zero
csrw satp, zero
# satp write with mstatus.TVM = 1
bseti t0, zero, 20
csrs mstatus, t0
csrw satp, zero
# STIMECMP from S mode
li t0, 1
ecall # enter S-mode
csrw stimecmp, zero
li t0, 3
ecall # return to M-mode
csrsi mcounteren, 2 # mcounteren_tm = 1
li t0, 1
ecall # supervisor mode again
csrw stimecmp, zero
li t0, 3
ecall # machine mode again
j done