cvw/wally-pipelined/src/muldiv
2021-10-19 12:09:43 -05:00
..
div replaced flopenl with flopenr when clearing to 0 2021-10-18 16:53:18 -07:00
div.sv More divider cleanup 2021-10-03 00:20:35 -04:00
intdivrestoring.sv add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
intdivrestoringstep.sv Reduced cycle count for DIVW/DIVUW by two 2021-10-03 09:42:22 -04:00
mul.sv Fixed multiplier and pointed arch tests to new path in addins 2021-10-18 15:43:59 -07:00
muldiv.sv Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
mult_cs.sv Some more sanitization but will pass to legal to determine if okay on version - it is substantially different in some ways but not a legal expert on this 2021-10-19 12:09:43 -05:00
redundantmul.sv Modify DW02_multp to properly list the correct number of bits at the output (i.e., 2*WIDTH + 2). 2021-10-19 11:58:06 -05:00