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cvw/synthDC
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Madeleine Masser-Frye f6a58f6f58 fixed plot naming and axes
2022-06-24 01:14:53 +00:00
..
scripts added flop as default driver and load 2022-06-24 00:51:09 +00:00
.synopsys_dc.setup added support for tsmc28, fixed ff modules/analysis for timing 2022-05-25 06:44:22 +00:00
bestSynths.csv latest synths and synth script 2022-06-17 19:34:58 +00:00
extractSummary.py fixed plot naming and axes 2022-06-24 01:14:53 +00:00
Makefile Default value of Drive in Makefile 2022-06-23 23:16:43 +00:00
oldBestSynths.csv fresh set of syntheses 2022-06-15 18:26:16 +00:00
oldPpaData.csv fresh set of syntheses 2022-06-15 18:26:16 +00:00
ppaAnalyze.py error calculation function, fixed energy units 2022-06-17 19:36:32 +00:00
ppaData.csv latest synths and synth script 2022-06-17 19:34:58 +00:00
ppaEquations.csv latest synths and synth script 2022-06-17 19:34:58 +00:00
ppaFitting.csv error calculation function, fixed energy units 2022-06-17 19:36:32 +00:00
ppaSynth.py latest synths and synth script 2022-06-17 19:34:58 +00:00
README.md Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
runConfigsSynth.sh wally synthesis analysis 2022-06-24 00:21:39 +00:00
runFrequencySynth.sh remove run deletion with wally synthesis 2022-06-17 19:45:38 +00:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.