James Stine f5e22fccbb update csrm to add dpc and dcsr		2024-06-10 17:31:14 -05:00
..
cache	Signal name changes to match book.	2024-06-02 16:32:25 -05:00
debug	minor comments	2024-06-09 18:53:51 -05:00
ebu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
fpu	add FP registers to debug scan chain	2024-06-07 23:18:44 -05:00
generic	remove unused file	2024-06-05 14:25:29 -05:00
hazard	clean up repo	2024-06-03 22:21:02 -05:00
ieu	Merge branch 'openhwgroup:main' into main	2024-06-09 13:42:53 -05:00
ifu	minor fix of DSCR naming comment	2024-06-09 10:43:43 -05:00
lsu	minor fix of DSCR naming comment	2024-06-09 10:43:43 -05:00
mdu	Remove additional bitwise operator	2024-05-15 09:29:54 -07:00
mmu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
privileged	update csrm to add dpc and dcsr	2024-06-10 17:31:14 -05:00
uncore	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
wally	add FP registers to debug scan chain	2024-06-07 23:18:44 -05:00
cvw.sv	cleanup of cvw top	2024-06-04 14:49:21 -05:00